Lines Matching +full:0 +full:x444
30 #define IMX95_CFG_LINK_IO_VAR 0x0
31 #define IO_VAR_16FF_16G_SERDES 0x1
32 #define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2))
34 #define IMX95_CFG_LINK_MII_PROT 0x4
35 #define CFG_LINK_MII_PORT_0 GENMASK(3, 0)
37 #define MII_PROT_MII 0x0
38 #define MII_PROT_RMII 0x1
39 #define MII_PROT_RGMII 0x2
40 #define MII_PROT_SERIAL 0x3
41 #define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2))
43 #define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4)
44 #define PCS_PROT_1G_SGMII BIT(0)
51 #define PRB_NETCRR 0x100
52 #define NETCRR_SR BIT(0)
55 #define PRB_NETCSR 0x104
56 #define NETCSR_ERROR BIT(0)
60 #define IERB_EMDIOFAUXR 0x344
61 #define IERB_T0FAUXR 0x444
62 #define IERB_EFAUXR(a) (0x3044 + 0x100 * (a))
63 #define IERB_VFAUXR(a) (0x4004 + 0x40 * (a))
64 #define FAUXR_LDID GENMASK(3, 0)
67 #define IMX95_ENETC0_BUS_DEVFN 0x0
68 #define IMX95_ENETC1_BUS_DEVFN 0x40
69 #define IMX95_ENETC2_BUS_DEVFN 0x80
72 #define NETC_HAS_NETCMIX BIT(0)
109 return (reg[0] >> 8) & 0xffff; in netc_of_pci_get_bus_devfn()
145 val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) | in imx95_netcmix_init()
155 if (bus_devfn < 0) in imx95_netcmix_init()
166 if (mii_proto < 0) in imx95_netcmix_init()
192 return 0; in imx95_netcmix_init()
214 netc_reg_write(priv->prb, PRB_NETCRR, 0); in netc_unlock_ierb_with_warm_reset()
225 netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0); in imx95_ierb_init()
227 netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0); in imx95_ierb_init()
229 netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1); in imx95_ierb_init()
247 return 0; in imx95_ierb_init()
276 return 0; in netc_ierb_init()
287 (val & NETCRR_LOCK) ? 1 : 0, in netc_prb_show()
288 (val & NETCRR_SR) ? 1 : 0); in netc_prb_show()
292 (val & NETCSR_STATE) ? 1 : 0, in netc_prb_show()
293 (val & NETCSR_ERROR) ? 1 : 0); in netc_prb_show()
295 return 0; in netc_prb_show()
334 return 0; in netc_prb_check_error()
411 if (netc_prb_check_error(priv) < 0) in netc_blk_ctrl_probe()
422 return 0; in netc_blk_ctrl_probe()