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/linux-6.14.4/drivers/gpu/drm/i915/soc/
Dintel_pch.h19 PCH_NONE = 0, /* No PCH present */
36 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
37 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
38 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
39 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
40 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
41 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
42 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
43 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
44 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux-6.14.4/drivers/media/i2c/
Dov5670.c22 #define OV5670_REG_CHIP_ID 0x300a
23 #define OV5670_CHIP_ID 0x005670
25 #define OV5670_REG_MODE_SELECT 0x0100
26 #define OV5670_MODE_STANDBY 0x00
27 #define OV5670_MODE_STREAMING 0x01
29 #define OV5670_REG_SOFTWARE_RST 0x0103
30 #define OV5670_SOFTWARE_RST 0x01
32 #define OV5670_MIPI_SC_CTRL0_REG 0x3018
39 #define OV5670_REG_VTS 0x380e
40 #define OV5670_VTS_30FPS 0x0808 /* default for 30 fps */
[all …]
Dov01a10.c22 #define OV01A10_REG_CHIP_ID 0x300a
23 #define OV01A10_CHIP_ID 0x560141
25 #define OV01A10_REG_MODE_SELECT 0x0100
26 #define OV01A10_MODE_STANDBY 0x00
27 #define OV01A10_MODE_STREAMING 0x01
36 #define OV01A10_REG_VTS 0x380e
37 #define OV01A10_VTS_DEF 0x0380
38 #define OV01A10_VTS_MIN 0x0380
39 #define OV01A10_VTS_MAX 0xffff
43 #define OV01A10_REG_EXPOSURE 0x3501
[all …]
Dimx415.c24 #define IMX415_PIXEL_ARRAY_TOP 0
25 #define IMX415_PIXEL_ARRAY_LEFT 0
32 #define IMX415_MODE CCI_REG8(0x3000)
33 #define IMX415_MODE_OPERATING (0)
34 #define IMX415_MODE_STANDBY BIT(0)
35 #define IMX415_REGHOLD CCI_REG8(0x3001)
36 #define IMX415_REGHOLD_INVALID (0)
37 #define IMX415_REGHOLD_VALID BIT(0)
38 #define IMX415_XMSTA CCI_REG8(0x3002)
39 #define IMX415_XMSTA_START (0)
[all …]
Dov5648.c30 #define OV5648_SW_STANDBY_REG 0x100
31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0)
33 #define OV5648_SW_RESET_REG 0x103
34 #define OV5648_SW_RESET_RESET BIT(0)
36 #define OV5648_PAD_OEN0_REG 0x3000
37 #define OV5648_PAD_OEN1_REG 0x3001
38 #define OV5648_PAD_OEN2_REG 0x3002
39 #define OV5648_PAD_OUT0_REG 0x3008
40 #define OV5648_PAD_OUT1_REG 0x3009
42 #define OV5648_CHIP_ID_H_REG 0x300a
[all …]
/linux-6.14.4/arch/mips/include/asm/sgi/
Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]
/linux-6.14.4/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux-6.14.4/sound/soc/codecs/
Drt5682s.h21 #define RT5682S_RESET 0x0000
22 #define RT5682S_VERSION_ID 0x00fd
23 #define RT5682S_VENDOR_ID 0x00fe
24 #define RT5682S_DEVICE_ID 0x00ff
26 #define RT5682S_HP_CTRL_1 0x0002
27 #define RT5682S_HP_CTRL_2 0x0003
28 #define RT5682S_HPL_GAIN 0x0005
29 #define RT5682S_HPR_GAIN 0x0006
31 #define RT5682S_I2C_CTRL 0x0008
34 #define RT5682S_CBJ_BST_CTRL 0x000b
[all …]
Drt5682s.c32 #define DEVICE_ID 0x6749
50 {RT5682S_I2C_CTRL, 0x0007},
51 {RT5682S_DIG_IN_CTRL_1, 0x0000},
52 {RT5682S_CHOP_DAC_2, 0x2020},
53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
55 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
56 {RT5682S_DEPOP_1, 0x0000},
57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
58 {RT5682S_DAC1_DIG_VOL, 0xfefe},
[all …]
/linux-6.14.4/drivers/net/ethernet/qlogic/qed/
Dqed_mfw_hsi.h9 #define MFW_TRACE_SIGNATURE 0x25071946
12 #define MFW_TRACE_EVENTID_MASK 0x00ffff
13 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
22 * 0 - just errors will be written to the buffer
24 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
53 #define OFFSIZE_OFFSET_SHIFT 0
54 #define OFFSIZE_OFFSET_MASK 0x0000ffff
57 #define OFFSIZE_SIZE_MASK 0xffff0000
77 #define ETH_SPEED_AUTONEG 0x0
78 #define ETH_SPEED_SMARTLINQ 0x8
[all …]
/linux-6.14.4/drivers/clk/qcom/
Dgcc-ipq806x.c33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
[all …]
Dmmcc-msm8994.c44 { P_XO, 0 },
54 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
91 { 1500000000, 2000000000, 0 },
95 { 500000000, 1500000000, 0 },
99 .post_div_mask = 0xf00,
103 .offset = 0x0,
108 .enable_reg = 0x100,
109 .enable_mask = BIT(0),
[all …]
Dmmcc-msm8998.c49 { 0x0, 1 },
50 { 0x1, 2 },
51 { 0x3, 4 },
52 { 0x7, 8 },
57 .offset = 0xc000,
60 .enable_reg = 0x1e0,
61 .enable_mask = BIT(0),
74 .offset = 0xc000,
89 .offset = 0xc050,
92 .enable_reg = 0x1e0,
[all …]
Dmmcc-msm8996.c64 { 1500000000, 2000000000, 0 },
70 { 1500000000, 2000000000, 0 },
74 { 500000000, 1500000000, 0 },
78 .offset = 0x0,
83 .enable_reg = 0x100,
84 .enable_mask = BIT(0),
97 .offset = 0x0,
112 .offset = 0x30,
117 .enable_reg = 0x100,
131 .offset = 0x30,
[all …]
/linux-6.14.4/drivers/media/platform/renesas/vsp1/
Dvsp1_regs.h17 #define VI6_CMD(n) (0x0000 + (n) * 4)
19 #define VI6_CMD_STRCMD BIT(0)
21 #define VI6_CLK_DCSWT 0x0018
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
24 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0)
25 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0
27 #define VI6_SRESET 0x0028
30 #define VI6_STATUS 0x0038
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12)
37 #define VI6_WPF_IRQ_ENB_FREE BIT(0)
[all …]
/linux-6.14.4/drivers/scsi/
Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux-6.14.4/drivers/mfd/
Dlpc_ich.c53 #define ACPIBASE 0x40
54 #define ACPIBASE_GPE_OFF 0x28
55 #define ACPIBASE_GPE_END 0x2f
56 #define ACPIBASE_SMI_OFF 0x30
57 #define ACPIBASE_SMI_END 0x33
58 #define ACPIBASE_PMC_OFF 0x08
59 #define ACPIBASE_PMC_END 0x0c
60 #define ACPIBASE_TCO_OFF 0x60
61 #define ACPIBASE_TCO_END 0x7f
62 #define ACPICTRL_PMCBASE 0x44
[all …]
/linux-6.14.4/drivers/net/dsa/microchip/
Dksz_common.c38 #define MIB_COUNTER_NUM 0x20
117 { 0x00, "rx" },
118 { 0x01, "rx_hi" },
119 { 0x02, "rx_undersize" },
120 { 0x03, "rx_fragments" },
121 { 0x04, "rx_oversize" },
122 { 0x05, "rx_jabbers" },
123 { 0x06, "rx_symbol_err" },
124 { 0x07, "rx_crc_err" },
125 { 0x08, "rx_align_err" },
[all …]
/linux-6.14.4/include/linux/
Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux-6.14.4/sound/soc/mediatek/mt8195/
Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux-6.14.4/sound/soc/mediatek/mt8188/
Dmt8188-reg.h14 #define AUDIO_TOP_CON0 (0x0000)
15 #define AUDIO_TOP_CON1 (0x0004)
16 #define AUDIO_TOP_CON2 (0x0008)
17 #define AUDIO_TOP_CON3 (0x000c)
18 #define AUDIO_TOP_CON4 (0x0010)
19 #define AUDIO_TOP_CON5 (0x0014)
20 #define AUDIO_TOP_CON6 (0x0018)
21 #define AFE_MAS_HADDR_MSB (0x0020)
22 #define AFE_MEMIF_ONE_HEART (0x0024)
23 #define AFE_MUX_SEL_CFG (0x0044)
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]

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