Lines Matching +full:0 +full:x3b00

22 #define OV01A10_REG_CHIP_ID		0x300a
23 #define OV01A10_CHIP_ID 0x560141
25 #define OV01A10_REG_MODE_SELECT 0x0100
26 #define OV01A10_MODE_STANDBY 0x00
27 #define OV01A10_MODE_STREAMING 0x01
36 #define OV01A10_REG_VTS 0x380e
37 #define OV01A10_VTS_DEF 0x0380
38 #define OV01A10_VTS_MIN 0x0380
39 #define OV01A10_VTS_MAX 0xffff
43 #define OV01A10_REG_EXPOSURE 0x3501
49 #define OV01A10_REG_ANALOG_GAIN 0x3508
50 #define OV01A10_ANAL_GAIN_MIN 0x100
51 #define OV01A10_ANAL_GAIN_MAX 0xffff
55 #define OV01A10_REG_DIGITAL_GAIN_B 0x350a
56 #define OV01A10_REG_DIGITAL_GAIN_GB 0x3510
57 #define OV01A10_REG_DIGITAL_GAIN_GR 0x3513
58 #define OV01A10_REG_DIGITAL_GAIN_R 0x3516
59 #define OV01A10_DGTL_GAIN_MIN 0
60 #define OV01A10_DGTL_GAIN_MAX 0x3ffff
65 #define OV01A10_REG_TEST_PATTERN 0x4503
67 #define OV01A10_LINK_FREQ_400MHZ_INDEX 0
70 #define OV01A10_REG_FORMAT1 0x3820
75 #define OV01A10_REG_X_WIN 0x3811
76 #define OV01A10_REG_Y_WIN 0x3813
104 {0x0103, 0x01},
105 {0x0302, 0x00},
106 {0x0303, 0x06},
107 {0x0304, 0x01},
108 {0x0305, 0xe0},
109 {0x0306, 0x00},
110 {0x0308, 0x01},
111 {0x0309, 0x00},
112 {0x030c, 0x01},
113 {0x0322, 0x01},
114 {0x0323, 0x06},
115 {0x0324, 0x01},
116 {0x0325, 0x68},
120 {0x3002, 0xa1},
121 {0x301e, 0xf0},
122 {0x3022, 0x01},
123 {0x3501, 0x03},
124 {0x3502, 0x78},
125 {0x3504, 0x0c},
126 {0x3508, 0x01},
127 {0x3509, 0x00},
128 {0x3601, 0xc0},
129 {0x3603, 0x71},
130 {0x3610, 0x68},
131 {0x3611, 0x86},
132 {0x3640, 0x10},
133 {0x3641, 0x80},
134 {0x3642, 0xdc},
135 {0x3646, 0x55},
136 {0x3647, 0x57},
137 {0x364b, 0x00},
138 {0x3653, 0x10},
139 {0x3655, 0x00},
140 {0x3656, 0x00},
141 {0x365f, 0x0f},
142 {0x3661, 0x45},
143 {0x3662, 0x24},
144 {0x3663, 0x11},
145 {0x3664, 0x07},
146 {0x3709, 0x34},
147 {0x370b, 0x6f},
148 {0x3714, 0x22},
149 {0x371b, 0x27},
150 {0x371c, 0x67},
151 {0x371d, 0xa7},
152 {0x371e, 0xe7},
153 {0x3730, 0x81},
154 {0x3733, 0x10},
155 {0x3734, 0x40},
156 {0x3737, 0x04},
157 {0x3739, 0x1c},
158 {0x3767, 0x00},
159 {0x376c, 0x81},
160 {0x3772, 0x14},
161 {0x37c2, 0x04},
162 {0x37d8, 0x03},
163 {0x37d9, 0x0c},
164 {0x37e0, 0x00},
165 {0x37e1, 0x08},
166 {0x37e2, 0x10},
167 {0x37e3, 0x04},
168 {0x37e4, 0x04},
169 {0x37e5, 0x03},
170 {0x37e6, 0x04},
171 {0x3800, 0x00},
172 {0x3801, 0x00},
173 {0x3802, 0x00},
174 {0x3803, 0x00},
175 {0x3804, 0x05},
176 {0x3805, 0x0f},
177 {0x3806, 0x03},
178 {0x3807, 0x2f},
179 {0x3808, 0x05},
180 {0x3809, 0x00},
181 {0x380a, 0x03},
182 {0x380b, 0x20},
183 {0x380c, 0x02},
184 {0x380d, 0xe8},
185 {0x380e, 0x03},
186 {0x380f, 0x80},
187 {0x3810, 0x00},
188 {0x3811, 0x08},
189 {0x3812, 0x00},
190 {0x3813, 0x08},
191 {0x3814, 0x01},
192 {0x3815, 0x01},
193 {0x3816, 0x01},
194 {0x3817, 0x01},
195 {0x3820, 0xa0},
196 {0x3822, 0x13},
197 {0x3832, 0x28},
198 {0x3833, 0x10},
199 {0x3b00, 0x00},
200 {0x3c80, 0x00},
201 {0x3c88, 0x02},
202 {0x3c8c, 0x07},
203 {0x3c8d, 0x40},
204 {0x3cc7, 0x80},
205 {0x4000, 0xc3},
206 {0x4001, 0xe0},
207 {0x4003, 0x40},
208 {0x4008, 0x02},
209 {0x4009, 0x19},
210 {0x400a, 0x01},
211 {0x400b, 0x6c},
212 {0x4011, 0x00},
213 {0x4041, 0x00},
214 {0x4300, 0xff},
215 {0x4301, 0x00},
216 {0x4302, 0x0f},
217 {0x4503, 0x00},
218 {0x4601, 0x50},
219 {0x4800, 0x64},
220 {0x481f, 0x34},
221 {0x4825, 0x33},
222 {0x4837, 0x11},
223 {0x4881, 0x40},
224 {0x4883, 0x01},
225 {0x4890, 0x00},
226 {0x4901, 0x00},
227 {0x4902, 0x00},
228 {0x4b00, 0x2a},
229 {0x4b0d, 0x00},
230 {0x450a, 0x04},
231 {0x450b, 0x00},
232 {0x5000, 0x65},
233 {0x5200, 0x18},
234 {0x5004, 0x00},
235 {0x5080, 0x40},
236 {0x0305, 0xf4},
237 {0x0325, 0xc2},
301 u8 data_buf[4] = {0}; in ov01a10_read_reg()
302 int ret = 0; in ov01a10_read_reg()
308 msgs[0].addr = client->addr; in ov01a10_read_reg()
309 msgs[0].flags = 0; in ov01a10_read_reg()
310 msgs[0].len = sizeof(addr_buf); in ov01a10_read_reg()
311 msgs[0].buf = addr_buf; in ov01a10_read_reg()
320 return ret < 0 ? ret : -EIO; in ov01a10_read_reg()
324 return 0; in ov01a10_read_reg()
331 int ret = 0; in ov01a10_write_reg()
341 return ret < 0 ? ret : -EIO; in ov01a10_write_reg()
343 return 0; in ov01a10_write_reg()
351 int ret = 0; in ov01a10_write_reg_list()
353 for (i = 0; i < r_list->num_of_regs; i++) { in ov01a10_write_reg_list()
358 "write reg 0x%4.4x err = %d\n", in ov01a10_write_reg_list()
364 return 0; in ov01a10_write_reg_list()
371 int ret = 0; in ov01a10_update_digital_gain()
401 return 0; in ov01a10_test_pattern()
408 /* for vflip and hflip, use 0x9 as window offset to keep the bayer */
414 offset = hflip ? 0x9 : 0x8; in ov01a10_set_hflip()
423 val = hflip ? val | FIELD_PREP(OV01A10_HFLIP_MASK, 0x1) : in ov01a10_set_hflip()
434 offset = vflip ? 0x9 : 0x8; in ov01a10_set_vflip()
443 val = vflip ? val | FIELD_PREP(OV01A10_VFLIP_MASK, 0x1) : in ov01a10_set_vflip()
455 int ret = 0; in ov01a10_set_ctrl()
467 return 0; in ov01a10_set_ctrl()
523 int ret = 0; in ov01a10_init_controls()
541 size - 1, 0, in ov01a10_init_controls()
547 V4L2_CID_PIXEL_RATE, 0, in ov01a10_init_controls()
582 0, 0, ov01a10_test_pattern_menu); in ov01a10_init_controls()
585 0, 1, 1, 0); in ov01a10_init_controls()
587 0, 1, 1, 0); in ov01a10_init_controls()
601 return 0; in ov01a10_init_controls()
623 int ret = 0; in ov01a10_start_streaming()
655 int ret = 0; in ov01a10_stop_streaming()
668 int ret = 0; in ov01a10_set_stream()
674 if (ret < 0) in ov01a10_set_stream()
728 return 0; in ov01a10_set_format()
744 return 0; in ov01a10_init_state()
751 if (code->index > 0) in ov01a10_enum_mbus_code()
756 return 0; in ov01a10_enum_mbus_code()
772 return 0; in ov01a10_enum_frame_size()
785 sel->r.top = 0; in ov01a10_get_selection()
786 sel->r.left = 0; in ov01a10_get_selection()
789 return 0; in ov01a10_get_selection()
798 return 0; in ov01a10_get_selection()
850 return 0; in ov01a10_identify_module()
869 int ret = 0; in ov01a10_probe()
883 ov01a10->cur_mode = &supported_modes[0]; in ov01a10_probe()
918 if (ret < 0) { in ov01a10_probe()
923 return 0; in ov01a10_probe()