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/linux-6.14.4/Documentation/devicetree/bindings/interconnect/
Dqcom,x1e80100-rpmh.yaml72 clk_virt: interconnect-0 {
80 reg = <0x016e0000 0x14400>;
Dqcom,sm8650-rpmh.yaml124 clk_virt: interconnect-0 {
132 reg = <0x016e0000 0x14400>;
Dqcom,sm8550-rpmh.yaml126 clk_virt: interconnect-0 {
134 reg = <0x016e0000 0x14400>;
/linux-6.14.4/drivers/net/ethernet/wangxun/libwx/
Dwx_type.h13 #define WX_NCSI_SUP 0x8000
14 #define WX_NCSI_MASK 0x8000
15 #define WX_WOL_SUP 0x4000
16 #define WX_WOL_MASK 0x4000
19 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
20 #define WX_PCI_LINK_STATUS 0xB2
24 #define WX_MIS_PWR 0x10000
25 #define WX_MIS_RST 0x1000C
27 #define WX_MIS_RST_SW_RST BIT(0)
28 #define WX_MIS_ST 0x10028
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/adreno/
Dadreno_gen7_2_0_snapshot.h99 {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
100 {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
101 {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
102 {A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
103 {A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
104 {A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
105 {A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
106 {A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
107 {A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
108 {A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
[all …]
Dadreno_gen7_9_0_snapshot.h121 { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
122 { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
123 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
124 { A7XX_SP_INST_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
125 { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
126 { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
127 { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
128 { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
129 { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
130 { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_11_0_offset.h29 // base address: 0x0
30 …NBCFG_SCRATCH_0 0x0068
31 …NBCFG_SCRATCH_1 0x006c
32 …NBCFG_SCRATCH_2 0x0070
33 …NBCFG_SCRATCH_3 0x0074
34 …NBCFG_SCRATCH_4 0x0078
38 // base address: 0x0
42 // base address: 0x0
43 …PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0580
47 // base address: 0x13b00000
[all …]
Dnbio_7_2_0_offset.h26 // base address: 0x0
27 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
28 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
29 …BIF_CFG_DEV0_RC_COMMAND 0x0004
30 …BIF_CFG_DEV0_RC_STATUS 0x0006
31 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
32 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
33 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
34 …BIF_CFG_DEV0_RC_BASE_CLASS 0x000b
35 …BIF_CFG_DEV0_RC_CACHE_LINE 0x000c
[all …]
Dnbio_7_7_0_offset.h29 // base address: 0x0
30 …NBCFG_SCRATCH_4 0x0078
34 // base address: 0x0
35 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
36 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
37 …BIF_CFG_DEV0_RC_COMMAND 0x0004
38 …BIF_CFG_DEV0_RC_STATUS 0x0006
39 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
40 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
41 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
Dsm8550.dtsi39 #clock-cells = <0>;
44 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0 0>;
72 clocks = <&cpufreq_hw 0>;
77 qcom,freq-domain = <&cpufreq_hw 0>;
97 reg = <0 0x100>;
[all …]
/linux-6.14.4/drivers/net/wireless/realtek/rtw89/
Dreg.h8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A
11 #define R_AX_SYS_ISO_CTRL 0x0000
17 #define R_AX_SYS_FUNC_EN 0x0002
19 #define B_AX_FEN_BBRSTB BIT(0)
21 #define R_AX_SYS_PW_CTRL 0x0004
36 #define R_AX_SYS_CLK_CTRL 0x0008
39 #define R_AX_SYS_SWR_CTRL1 0x0010
42 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
46 #define R_AX_RSV_CTRL 0x001C
50 #define R_AX_AFE_LDO_CTRL 0x0020
[all …]