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/linux-6.14.4/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
17 reg = <0>;
61 reg = <0x6011000 0x20>;
70 reg = <0x10000000 0x4000000>;
75 #address-cells = <0>;
83 <0x00003 0x00003 0x00000008>,
84 <0x00004 0x00004 0x00000010>,
85 <0x00005 0x00005 0x00000200>,
86 <0x00006 0x00006 0x00000100>,
[all …]
/linux-6.14.4/arch/powerpc/include/asm/
Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/linux-6.14.4/arch/parisc/include/uapi/asm/
Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/linux-6.14.4/include/uapi/asm-generic/
Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/linux-6.14.4/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi10 #clock-cells = <0>;
17 #clock-cells = <0>;
24 #clock-cells = <0>;
31 #clock-cells = <0>;
38 reg = <0 0xe0700000 0 0x80000>,
39 <0 0xe0780000 0 0x80000>,
40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
43 interrupts = <0 325 4>,
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/registers/display/
Ddsi_phy_28nm_8960.xml9 <array offset="0x00000" name="LN" length="4" stride="0x40">
10 <reg32 offset="0x00" name="CFG_0"/>
11 <reg32 offset="0x04" name="CFG_1"/>
12 <reg32 offset="0x08" name="CFG_2"/>
13 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
14 <reg32 offset="0x14" name="TEST_STR_0"/>
15 <reg32 offset="0x18" name="TEST_STR_1"/>
18 <reg32 offset="0x00100" name="LNCK_CFG_0"/>
19 <reg32 offset="0x00104" name="LNCK_CFG_1"/>
20 <reg32 offset="0x00108" name="LNCK_CFG_2"/>
[all …]
Dhdmi.xml15 <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
25 <value name="DDC_WRITE" value="0"/>
29 <value name="ACR_NONE" value="0"/>
36 <value name="CEC_TX_OK" value="0"/>
42 <reg32 offset="0x00000" name="CTRL">
43 <bitfield name="ENABLE" pos="0" type="boolean"/>
47 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
48 <bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
50 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
54 acr_pck_ctrl_reg |= 0x80000100;
[all …]
Ddsi_phy_28nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
Ddsi_phy_20nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
[all …]
Ddsi_phy_10nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
[all …]
Ddsi_phy_14nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0">
16 <reg32 offset="0x00014" name="CLK_CFG1">
17 <bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
19 <reg32 offset="0x00018" name="GLBL_TEST_CTRL">
22 <reg32 offset="0x0001C" name="CTRL_0"/>
23 <reg32 offset="0x00020" name="CTRL_1">
[all …]
/linux-6.14.4/arch/mips/include/uapi/asm/
Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/linux-6.14.4/arch/x86/events/
Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/linux-6.14.4/arch/powerpc/include/asm/nohash/32/
Dpte-85xx.h12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
20 #define _PAGE_READ 0x00001 /* H: Read permission (SR) */
21 #define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */
22 #define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */
23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */
24 #define _PAGE_EXEC 0x00010 /* H: SX permission */
25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
28 #define _PAGE_GUARDED 0x00080 /* H: G bit */
29 #define _PAGE_COHERENT 0x00100 /* H: M bit */
[all …]
/linux-6.14.4/drivers/gpu/drm/arm/
Dmalidp_regs.h20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
50 #define MALIDP550_SE_IRQ_EOW (1 << 0)
54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
67 #define MALIDP_CFG_VALID (1 << 0)
68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
75 #define MALIDP_REG_STATUS 0x00000
76 #define MALIDP_REG_SETIRQ 0x00004
77 #define MALIDP_REG_MASKIRQ 0x00008
78 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Damd-xgbe.txt32 0 - 1GbE and 10GbE (default)
44 0 - Off
55 reg = <0 0xe0700000 0 0x80000>,
56 <0 0xe0780000 0 0x80000>,
57 <0 0xe1240800 0 0x00400>,
58 <0 0xe1250000 0 0x00060>,
59 <0 0xe1250080 0 0x00004>;
61 interrupts = <0 325 4>,
62 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
63 <0 323 4>;
[all …]
/linux-6.14.4/arch/powerpc/include/uapi/asm/
Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/linux-6.14.4/arch/riscv/boot/dts/thead/
Dth1520.dtsi17 #size-cells = <0>;
20 c910_0: cpu@0 {
27 reg = <0>;
129 <0x00003 0x00003 0x0007fff8>,
130 <0x00004 0x00004 0x0007fff8>,
131 <0x00005 0x00005 0x0007fff8>,
132 <0x00006 0x00006 0x0007fff8>,
133 <0x00007 0x00007 0x0007fff8>,
134 <0x00008 0x00008 0x0007fff8>,
135 <0x00009 0x00009 0x0007fff8>,
[all …]
/linux-6.14.4/arch/alpha/include/uapi/asm/
Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
/linux-6.14.4/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dvmmnv04.c31 u32 data = addr | 0x00000003; /* PRESENT, RW. */ in nv04_vmm_pgt_pte()
34 data += 0x00001000; in nv04_vmm_pgt_pte()
52 VMM_WO032(pt, vmm, 8 + (ptei++ * 4), *map->dma++ | 0x00000003); in nv04_vmm_pgt_dma()
63 VMM_FO032(pt, vmm, 8 + (ptei * 4), 0, ptes); in nv04_vmm_pgt_unmap()
75 { PGT, 15, 4, 0x1000, &nv04_vmm_desc_pgt },
96 { 12, &nv04_vmm_desc_12[0], NVKM_VMM_PAGE_HOST },
135 mem = vmm->pd->pt[0]->memory; in nv04_vmm_new()
137 nvkm_wo32(mem, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ in nv04_vmm_new()
138 nvkm_wo32(mem, 0x00004, vmm->limit - 1); in nv04_vmm_new()
140 return 0; in nv04_vmm_new()
/linux-6.14.4/arch/x86/include/asm/
Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_DELIVERY_MODE_FIXED 0
30 #define APIC_ID 0x20
32 #define APIC_LVR 0x30
33 #define APIC_LVR_MASK 0xFF00FF
35 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
36 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
38 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
42 #define APIC_XAPIC(x) ((x) >= 0x14)
[all …]
/linux-6.14.4/arch/sparc/include/uapi/asm/
Dtermbits.h51 #define VINTR 0
78 #define IUCLC 0x0200
79 #define IXON 0x0400
80 #define IXOFF 0x1000
81 #define IMAXBEL 0x2000
82 #define IUTF8 0x4000
85 #define OLCUC 0x00002
86 #define ONLCR 0x00004
87 #define NLDLY 0x00100
88 #define NL0 0x00000
[all …]
/linux-6.14.4/include/linux/perf/
Darm_pmu.h31 #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
32 #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
33 #define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */
39 #define HW_OP_UNSUPPORTED 0xFFFF
41 #define CACHE_OP_UNSUPPORTED 0xFFFF
44 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
47 [0 ... C(MAX) - 1] = { \
48 [0 ... C(OP_MAX) - 1] = { \
49 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
62 * an event. A 0 means that the counter can be used.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux-6.14.4/drivers/gpu/drm/v3d/
Dv3d_regs.h14 WARN_ON((fieldval & ~field##_MASK) != 0); \
22 WARN_ON((fieldval & ~field##_MASK(_ver)) != 0); \
31 #define V3D_HUB_AXICFG 0x00000
32 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
33 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
34 #define V3D_HUB_UIFCFG 0x00004
35 #define V3D_HUB_IDENT0 0x00008
37 #define V3D_HUB_IDENT1 0x0000c
48 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
49 # define V3D_HUB_IDENT1_TVER_SHIFT 0
[all …]

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