Lines Matching +full:0 +full:x00004
14 WARN_ON((fieldval & ~field##_MASK) != 0); \
22 WARN_ON((fieldval & ~field##_MASK(_ver)) != 0); \
31 #define V3D_HUB_AXICFG 0x00000
32 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
33 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
34 #define V3D_HUB_UIFCFG 0x00004
35 #define V3D_HUB_IDENT0 0x00008
37 #define V3D_HUB_IDENT1 0x0000c
48 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
49 # define V3D_HUB_IDENT1_TVER_SHIFT 0
51 #define V3D_HUB_IDENT2 0x00010
53 # define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0)
54 # define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0
56 #define V3D_HUB_IDENT3 0x00014
59 # define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0)
60 # define V3D_HUB_IDENT3_IPIDX_SHIFT 0
62 #define V3D_HUB_INT_STS 0x00050
63 #define V3D_HUB_INT_SET 0x00054
64 #define V3D_HUB_INT_CLR 0x00058
65 #define V3D_HUB_INT_MSK_STS 0x0005c
66 #define V3D_HUB_INT_MSK_SET 0x00060
67 #define V3D_HUB_INT_MSK_CLR 0x00064
74 # define V3D_HUB_INT_TFUF BIT(0)
77 #define V3D_GCA_CACHE_CTRL 0x0000c
78 # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0)
80 #define V3D_GCA_SAFE_SHUTDOWN 0x000b0
81 # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0)
83 #define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4
86 # define V3D_TOP_GR_BRIDGE_REVISION 0x00000
89 # define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0)
90 # define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0
93 # define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008
94 # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0)
96 # define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c
97 # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
99 #define V3D_TFU_CS(ver) ((ver >= 71) ? 0x00700 : 0x00400)
107 # define V3D_TFU_CS_BUSY BIT(0)
109 #define V3D_TFU_SU(ver) ((ver >= 71) ? 0x00704 : 0x00404)
110 /* Interrupt when FINTTHR input slots are free (0 = disabled) */
115 /* skips writes, computes CRC of the image. miplevels must be 0. */
117 # define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0)
118 # define V3D_TFU_SU_THROTTLE_SHIFT 0
120 #define V3D_TFU_ICFG(ver) ((ver >= 71) ? 0x00708 : 0x00408)
122 # define V3D_TFU_ICFG_IOC BIT(0)
125 #define V3D_TFU_IIA(ver) ((ver >= 71) ? 0x0070c : 0x0040c)
127 #define V3D_TFU_ICA(ver) ((ver >= 71) ? 0x00710 : 0x00410)
129 #define V3D_TFU_IIS(ver) ((ver >= 71) ? 0x00714 : 0x00414)
131 #define V3D_TFU_IUA(ver) ((ver >= 71) ? 0x00718 : 0x00418)
133 #define V3D_V7_TFU_IOC 0x0071c
135 #define V3D_TFU_IOA(ver) ((ver >= 71) ? 0x00720 : 0x0041c)
137 #define V3D_TFU_IOS(ver) ((ver >= 71) ? 0x00724 : 0x00420)
138 /* TFU YUV Coefficient 0 */
139 #define V3D_TFU_COEF0(ver) ((ver >= 71) ? 0x00728 : 0x00424)
143 #define V3D_TFU_COEF1(ver) ((ver >= 71) ? 0x0072c : 0x00428)
145 #define V3D_TFU_COEF2(ver) ((ver >= 71) ? 0x00730 : 0x0042c)
147 #define V3D_TFU_COEF3(ver) ((ver >= 71) ? 0x00734 : 0x00430)
150 #define V3D_TFU_CRC 0x00434
154 #define V3D_MMUC_CONTROL 0x01000
158 # define V3D_MMUC_CONTROL_ENABLE BIT(0)
160 #define V3D_MMU_CTL 0x01200
178 # define V3D_MMU_CTL_ENABLE BIT(0)
180 #define V3D_MMU_PT_PA_BASE 0x01204
181 #define V3D_MMU_HIT 0x01208
182 #define V3D_MMU_MISSES 0x0120c
183 #define V3D_MMU_STALLS 0x01210
185 #define V3D_MMU_ADDR_CAP 0x01214
187 # define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0)
188 # define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0
190 #define V3D_MMU_SHOOT_DOWN 0x01218
193 # define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0)
194 # define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0
196 #define V3D_MMU_BYPASS_START 0x0121c
197 #define V3D_MMU_BYPASS_END 0x01220
200 #define V3D_MMU_VIO_ID 0x0122c
203 #define V3D_MMU_ILLEGAL_ADDR 0x01230
207 #define V3D_MMU_VIO_ADDR 0x01234
209 #define V3D_MMU_DEBUG_INFO 0x01238
214 # define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
215 # define V3D_MMU_VERSION_SHIFT 0
219 #define V3D_CTL_IDENT0 0x00000
223 #define V3D_CTL_IDENT1 0x00004
235 # define V3D_IDENT1_REV_MASK V3D_MASK(3, 0)
236 # define V3D_IDENT1_REV_SHIFT 0
238 #define V3D_CTL_IDENT2 0x00008
241 #define V3D_CTL_MISCCFG 0x00018
244 # define V3D_MISCCFG_OVRTMUOUT BIT(0)
246 #define V3D_CTL_L2CACTL 0x00020
249 # define V3D_L2CACTL_L2CENA BIT(0)
251 #define V3D_CTL_SLCACTL 0x00024
258 # define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0)
259 # define V3D_SLCACTL_ICC_SHIFT 0
261 #define V3D_CTL_L2TCACTL 0x00030
264 # define V3D_L2TCACTL_FLM_FLUSH 0
271 # define V3D_L2TCACTL_L2TFLS BIT(0)
272 #define V3D_CTL_L2TFLSTA 0x00034
273 #define V3D_CTL_L2TFLEND 0x00038
275 #define V3D_CTL_INT_STS 0x00050
276 #define V3D_CTL_INT_SET 0x00054
277 #define V3D_CTL_INT_CLR 0x00058
278 #define V3D_CTL_INT_MSK_STS 0x0005c
279 #define V3D_CTL_INT_MSK_SET 0x00060
280 #define V3D_CTL_INT_MSK_CLR 0x00064
290 # define V3D_INT_FRDONE BIT(0)
292 #define V3D_CLE_CT0CS 0x00100
293 #define V3D_CLE_CT1CS 0x00104
295 #define V3D_CLE_CT0EA 0x00108
296 #define V3D_CLE_CT1EA 0x0010c
298 #define V3D_CLE_CT0CA 0x00110
299 #define V3D_CLE_CT1CA 0x00114
301 #define V3D_CLE_CT0RA 0x00118
302 #define V3D_CLE_CT1RA 0x0011c
304 #define V3D_CLE_CT0LC 0x00120
305 #define V3D_CLE_CT1LC 0x00124
306 #define V3D_CLE_CT0PC 0x00128
307 #define V3D_CLE_CT1PC 0x0012c
308 #define V3D_CLE_PCS 0x00130
309 #define V3D_CLE_BFC 0x00134
310 #define V3D_CLE_RFC 0x00138
311 #define V3D_CLE_TFBC 0x0013c
312 #define V3D_CLE_TFIT 0x00140
313 #define V3D_CLE_CT1CFG 0x00144
314 #define V3D_CLE_CT1TILECT 0x00148
315 #define V3D_CLE_CT1TSKIP 0x0014c
316 #define V3D_CLE_CT1PTCT 0x00150
317 #define V3D_CLE_CT0SYNC 0x00154
318 #define V3D_CLE_CT1SYNC 0x00158
319 #define V3D_CLE_CT0QTS 0x0015c
321 #define V3D_CLE_CT0QBA 0x00160
322 #define V3D_CLE_CT1QBA 0x00164
324 #define V3D_CLE_CT0QEA 0x00168
325 #define V3D_CLE_CT1QEA 0x0016c
327 #define V3D_CLE_CT0QMA 0x00170
328 #define V3D_CLE_CT0QMS 0x00174
329 #define V3D_CLE_CT1QCFG 0x00178
337 # define V3D_CLE_QCFG_MCDIS BIT(0)
339 #define V3D_PTB_BPCA 0x00300
340 #define V3D_PTB_BPCS 0x00304
341 #define V3D_PTB_BPOA 0x00308
342 #define V3D_PTB_BPOS 0x0030c
344 #define V3D_PTB_BXCF 0x00310
346 # define V3D_PTB_BXCF_CLIPDISA BIT(0)
348 #define V3D_V3_PCTR_0_EN 0x00674
350 #define V3D_V4_PCTR_0_EN 0x00650
351 /* When a bit is set, resets the counter to 0. */
352 #define V3D_V3_PCTR_0_CLR 0x00670
353 #define V3D_V4_PCTR_0_CLR 0x00654
354 #define V3D_PCTR_0_OVERFLOW 0x00658
356 #define V3D_V3_PCTR_0_PCTRS0 0x00684
357 #define V3D_V3_PCTR_0_PCTRS15 0x00660
361 #define V3D_V4_PCTR_0_SRC_0_3 0x00660
362 #define V3D_V4_PCTR_0_SRC_28_31 0x0067c
365 # define V3D_PCTR_S0_MASK(ver) (((ver) >= 71) ? V3D_MASK(7, 0) : V3D_MASK(6, 0))
366 # define V3D_PCTR_S0_SHIFT(ver) 0
374 #define V3D_PCTR_CYCLE_COUNT(ver) ((ver >= 71) ? 0 : 32)
377 #define V3D_PCTR_0_PCTR0 0x00680
378 #define V3D_PCTR_0_PCTR31 0x006fc
381 #define V3D_GMP_STATUS(ver) ((ver >= 71) ? 0x00600 : 0x00800)
392 # define V3D_GMP_STATUS_VIO BIT(0)
394 #define V3D_GMP_CFG(ver) ((ver >= 71) ? 0x00604 : 0x00804)
398 # define V3D_GMP_CFG_PROT_ENABLE BIT(0)
400 #define V3D_GMP_VIO_ADDR(ver) ((ver >= 71) ? 0x00608 : 0x00808)
401 #define V3D_GMP_VIO_TYPE 0x0080c
402 #define V3D_GMP_TABLE_ADDR 0x00810
403 #define V3D_GMP_CLEAR_LOAD 0x00814
404 #define V3D_GMP_PRESERVE_LOAD 0x00818
405 #define V3D_GMP_VALID_LINES 0x00820
407 #define V3D_CSD_STATUS 0x00900
413 # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
415 #define V3D_CSD_QUEUED_CFG0(ver) ((ver >= 71) ? 0x00930 : 0x00904)
418 # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0)
419 # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0
421 #define V3D_CSD_QUEUED_CFG1(ver) ((ver >= 71) ? 0x00934 : 0x00908)
424 # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0)
425 # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0
427 #define V3D_CSD_QUEUED_CFG2(ver) ((ver >= 71) ? 0x00938 : 0x0090c)
430 # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0)
431 # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0
433 #define V3D_CSD_QUEUED_CFG3(ver) ((ver >= 71) ? 0x0093c : 0x00910)
441 # define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0)
442 # define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0
445 #define V3D_CSD_QUEUED_CFG4(ver) ((ver >= 71) ? 0x00940 : 0x00914)
448 #define V3D_CSD_QUEUED_CFG5(ver) ((ver >= 71) ? 0x00944 : 0x00918)
451 #define V3D_CSD_QUEUED_CFG6(ver) ((ver >= 71) ? 0x00948 : 0x0091c)
454 #define V3D_V7_CSD_QUEUED_CFG7 0x0094c
456 #define V3D_CSD_CURRENT_CFG0(ver) ((ver >= 71) ? 0x00958 : 0x00920)
457 #define V3D_CSD_CURRENT_CFG1(ver) ((ver >= 71) ? 0x0095c : 0x00924)
458 #define V3D_CSD_CURRENT_CFG2(ver) ((ver >= 71) ? 0x00960 : 0x00928)
459 #define V3D_CSD_CURRENT_CFG3(ver) ((ver >= 71) ? 0x00964 : 0x0092c)
460 #define V3D_CSD_CURRENT_CFG4(ver) ((ver >= 71) ? 0x00968 : 0x00930)
461 #define V3D_CSD_CURRENT_CFG5(ver) ((ver >= 71) ? 0x0096c : 0x00934)
462 #define V3D_CSD_CURRENT_CFG6(ver) ((ver >= 71) ? 0x00970 : 0x00938)
464 #define V3D_V7_CSD_CURRENT_CFG7 0x00974
466 #define V3D_CSD_CURRENT_ID0(ver) ((ver >= 71) ? 0x00978 : 0x0093c)
471 # define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0)
472 # define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0
474 #define V3D_CSD_CURRENT_ID1(ver) ((ver >= 71) ? 0x0097c : 0x00940)
477 # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0)
478 # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0
480 #define V3D_ERR_FDBGO 0x00f04
481 #define V3D_ERR_FDBGB 0x00f08
482 #define V3D_ERR_FDBGR 0x00f0c
484 #define V3D_ERR_FDBGS 0x00f10
498 # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
500 #define V3D_ERR_STAT 0x00f20
516 # define V3D_ERR_VPAEABB BIT(0)