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/aosp_15_r20/external/deqp-deps/glslang/Test/baseResults/
Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/aosp_15_r20/external/angle/third_party/glslang/src/Test/baseResults/
H A Dspv.vulkan100.subgroupPartitioned.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:23: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:28: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:31: 'subgroup op' : requires SPIR-V 1.3
[all …]
H A Dspv.vulkan100.subgroupArithmetic.comp.out2 ERROR: 0:19: 'subgroup op' : requires SPIR-V 1.3
3 ERROR: 0:20: 'subgroup op' : requires SPIR-V 1.3
4 ERROR: 0:21: 'subgroup op' : requires SPIR-V 1.3
5 ERROR: 0:22: 'subgroup op' : requires SPIR-V 1.3
6 ERROR: 0:24: 'subgroup op' : requires SPIR-V 1.3
7 ERROR: 0:25: 'subgroup op' : requires SPIR-V 1.3
8 ERROR: 0:26: 'subgroup op' : requires SPIR-V 1.3
9 ERROR: 0:27: 'subgroup op' : requires SPIR-V 1.3
10 ERROR: 0:29: 'subgroup op' : requires SPIR-V 1.3
11 ERROR: 0:30: 'subgroup op' : requires SPIR-V 1.3
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/Support/
DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
85 "says the instruction applies in 64-bit mode but no more") \
87 "requires an OPSIZE prefix, so operands change width") \
89 "requires an ADSIZE prefix, so operands change width") \
90 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
96 "requires an OPSIZE prefix, so operands change width") \
98 "requires an OPSIZE prefix, so operands change width") \
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/Support/
DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
85 "says the instruction applies in 64-bit mode but no more") \
87 "requires an OPSIZE prefix, so operands change width") \
89 "requires an ADSIZE prefix, so operands change width") \
90 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
96 "requires an OPSIZE prefix, so operands change width") \
98 "requires an OPSIZE prefix, so operands change width") \
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/Support/
DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
85 "says the instruction applies in 64-bit mode but no more") \
87 "requires an OPSIZE prefix, so operands change width") \
89 "requires an ADSIZE prefix, so operands change width") \
90 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
96 "requires an OPSIZE prefix, so operands change width") \
98 "requires an OPSIZE prefix, so operands change width") \
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/Support/
DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
85 "says the instruction applies in 64-bit mode but no more") \
87 "requires an OPSIZE prefix, so operands change width") \
89 "requires an ADSIZE prefix, so operands change width") \
90 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
96 "requires an OPSIZE prefix, so operands change width") \
98 "requires an OPSIZE prefix, so operands change width") \
[all …]
/aosp_15_r20/external/capstone/arch/X86/
H A DX86DisassemblerDecoderCommon.h1 /*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
8 *===----------------------------------------------------------------------===*
15 *===----------------------------------------------------------------------===*/
18 /* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
22 * the decoder and the table generator in a C-friendly manner.
79 "64-bit mode but no more") \
80 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
82 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
84 ENUM_ENTRY(IC_OF, 2, "requires 0f prefix ") \
85 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/Support/
H A DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
79 "64-bit mode but no more") \
80 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
82 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
84 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
89 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
91 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
H A DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
75 "64-bit mode but no more") \
76 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
78 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
80 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
85 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
87 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
[all …]
/aosp_15_r20/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoderCommon.h1 //===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
8 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
80 "64-bit mode but no more") \
81 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
83 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
85 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
90 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
92 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
94 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
[all …]
/aosp_15_r20/external/llvm/test/MC/ARM/
H A Ddirective-arch_extension-fp.s1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
2 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
3 @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
4 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
5 @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
6 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
7 @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
8 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
13 @ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture
14 @ CHECK-V7-NEXT: .arch_extension fp
[all …]
H A Dfullfp16-neon-neg.s1 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileC…
2 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileC…
3 @ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | Fil…
4 @ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | Fil…
8 @ CHECK: error: instruction requires:
9 @ CHECK: error: instruction requires:
13 @ CHECK: error: instruction requires:
14 @ CHECK: error: instruction requires:
18 @ CHECK: error: instruction requires:
19 @ CHECK: error: instruction requires:
[all …]
H A Ddirective-arch_extension-simd.s1 @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \
2 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
3 @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \
4 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
5 @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \
6 @ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK
7 @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \
8 @ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK
13 @ CHECK-V7: error: architectural extension 'simd' is not allowed for the current base architecture
14 @ CHECK-V7-NEXT: .arch_extension simd
[all …]
H A Dfullfp16-neg.s1 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
2 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 |…
5 @ CHECK: error: instruction requires:
8 @ CHECK: error: instruction requires:
11 @ CHECK: error: instruction requires:
14 @ CHECK: error: instruction requires:
17 @ CHECK: error: instruction requires:
20 @ CHECK: error: instruction requires:
23 @ CHECK: error: instruction requires:
26 @ CHECK: error: instruction requires:
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td1 //===-------------------------------------------------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
15 (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
17 (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>;
19 (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
21 (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
23 (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
25 (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonDepMappings.td1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
79 def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= #$II", (L4_isub_memopb_io IntRegs:$Rs32, …
80 def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= #$II", (L4_isub_memoph_io IntRegs:$Rs32, …
81 def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= #$II", (L4_isub_memopw_io IntRegs:$Rs32, …
91 def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= $Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0…
92 def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= $Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0…
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
17 (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>;
19 (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
25 (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonDepMappings.td1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
79 def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= #$II", (L4_isub_memopb_io IntRegs:$Rs32, …
80 def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= #$II", (L4_isub_memoph_io IntRegs:$Rs32, …
81 def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= #$II", (L4_isub_memopw_io IntRegs:$Rs32, …
91 def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= $Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0…
92 def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= $Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0…
[all …]
/aosp_15_r20/external/llvm/test/MC/AArch64/
H A Dfullfp16-neon-neg.s1 // RUN: not llvm-mc -triple=aarch64 -mattr=+neon,-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
2 // RUN: not llvm-mc -triple=aarch64 -mattr=-neon,+fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
5 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
7 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
9 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
11 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
13 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
15 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
17 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
19 // CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: instruction requires:
[all …]
/aosp_15_r20/external/llvm/test/MC/Mips/
H A Dtarget-soft-float.s1 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+soft-float 2>&1 |\
2 # RUN: FileCheck %s --check-prefix=32
3 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips64 -mattr=+soft-float 2>&1 |\
4 # RUN: FileCheck %s --check-prefix=64
5 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+soft-float 2>&1 |\
6 # RUN: FileCheck %s --check-prefix=R2
7 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=+soft-float 2>&1 |\
8 # RUN: FileCheck %s --check-prefix=R6
12 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
14 # 64: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
[all …]
/aosp_15_r20/external/llvm/test/MC/Mips/mips32r2/
H A Dinvalid-dspr2.s3 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding \
4 # RUN: -mcpu=mips32r2 2>%t1
8 …absq_s.ph $8,$a0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
9 …absq_s.qb $15,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
10 …absq_s.w $s3,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
11 …addq.ph $s1,$15,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
12 …addq_s.ph $s3,$s6,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
13 …addq_s.w $a2,$8,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
14 …addqh.ph $s4,$14,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
15 …addqh_r.ph $sp,$25,$s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU f…
[all …]
/aosp_15_r20/external/llvm/test/MC/SystemZ/
H A Dinsn-bad-zEC12.s2 # RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 < %s 2> %t
5 #CHECK: error: {{(instruction requires: vector)?}}
11 #CHECK: ntstg %r0, -524289
15 ntstg %r0, -524289
19 #CHECK: ppa %r0, %r0, -1
23 ppa %r0, %r0, -1
27 #CHECK: risbgn %r0,%r0,0,0,-1
31 #CHECK: risbgn %r0,%r0,0,-1,0
35 #CHECK: risbgn %r0,%r0,-1,0,0
39 risbgn %r0,%r0,0,0,-1
[all …]
/aosp_15_r20/prebuilts/sdk/current/androidx/m2repository/androidx/navigation/navigation-compose/2.9.0-alpha04/
H A Dnavigation-compose-2.9.0-alpha04.module5 "module": "navigation-compose",
6 "version": "2.9.0-alpha04",
24 "org.gradle.usage": "java-runtime"
29 "module": "navigation-common",
31 "requires": "2.9.0-alpha04"
33 "reason": "navigation-compose is in atomic group androidx.navigation"
37 "module": "navigation-common-ktx",
39 "requires": "2.9.0-alpha04"
41 "reason": "navigation-compose is in atomic group androidx.navigation"
45 "module": "navigation-dynamic-features-fragment",
[all …]

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