| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 414 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
589 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
652 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
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| H A D | R600InstrInfo.cpp | 1241 unsigned Src0Reg, in buildDefaultInstruction()
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| H A D | AMDGPURegisterBankInfo.cpp | 2994 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
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| H A D | SIInstrInfo.cpp | 4114 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
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| /aosp_15_r20/external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4482 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4546 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4560 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4761 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4661 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4725 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4739 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4940 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4585 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4644 Register Src0Reg = getRegForValue(Src0); in selectMul() local
4657 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4852 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectSDiv() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 428 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
835 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
1071 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
1352 Register Src0Reg = in selectIntrinsicCmp() local
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| H A D | R600InstrInfo.cpp | 1215 unsigned Src0Reg, in buildDefaultInstruction()
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| H A D | AMDGPURegisterBankInfo.cpp | 4322 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
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| H A D | AMDGPULegalizerInfo.cpp | 2100 Register Src0Reg = MI.getOperand(1).getReg(); in legalizeFrem() local
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| H A D | SIInstrInfo.cpp | 5280 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 1264 unsigned Src0Reg, in buildDefaultInstruction()
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| H A D | SIInstrInfo.cpp | 2108 unsigned Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1932 Register Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1941 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
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| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1684 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2595 Register Src0Reg = MI.getOperand(2).getReg(); in fewerElementsVectorCmp() local
4199 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6581 Register Src0Reg = MI.getOperand(1).getReg(); in lowerMergeValues() local
6733 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local
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