| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 130 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0, in offsetsCanBeCombined()
181 unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff; in findMatchingDSInst() local
205 unsigned Offset0 in mergeRead2Pair() local
301 unsigned Offset0 in mergeWrite2Pair() local
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| H A D | AMDGPUInstrInfo.cpp | 51 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
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| H A D | SIInstrInfo.cpp | 94 int64_t &Offset0, in areLoadsFromSameBasePtr()
231 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOpBaseRegImmOfs() local
1344 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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| H A D | AMDGPUISelDAGToDAG.cpp | 719 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 192 int64_t Offset0 = 0; in getHazardType() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1127 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal()
1146 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
1152 SDValue &Offset0, in SelectDS128Bit8ByteAligned()
1158 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2()
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| H A D | SIInstrInfo.cpp | 173 int64_t &Offset0, in areLoadsFromSameBasePtr()
332 unsigned Offset0 = Offset0Op->getImm(); in getMemOperandsWithOffsetWidth() local
525 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
3274 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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| H A D | AMDGPUInstructionSelector.cpp | 1545 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
4276 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal()
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| H A D | SIISelLowering.cpp | 7299 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 277 int64_t Offset0; in apply() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 397 int64_t Offset0; in apply() local
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| H A D | HexagonISelLoweringHVX.cpp | 2196 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 147 int64_t &Offset0, in areLoadsFromSameBasePtr()
294 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOperandWithOffset() local
505 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear()
2531 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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| H A D | AMDGPUInstructionSelector.cpp | 1080 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
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| H A D | AMDGPUISelDAGToDAG.cpp | 1259 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
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| H A D | SIISelLowering.cpp | 6199 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1304 APInt Offset0(IndexWidth, 0); in ConstantFoldCompareInstOperands() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 17043 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
19231 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
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| /aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 9847 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 13961 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8545 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
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