Lines Matching defs:tx_intf_driver_api
70 struct tx_intf_driver_api { struct
71 …num tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type);
73 u32 (*reg_read)(u32 reg);
74 void (*reg_write)(u32 reg, u32 value);
76 u32 (*TX_INTF_REG_MULTI_RST_read)(void);
77 u32 (*TX_INTF_REG_ARBITRARY_IQ_read)(void);
78 u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
79 u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
80 u32 (*TX_INTF_REG_CSI_FUZZER_read)(void);
81 u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
82 u32 (*TX_INTF_REG_ARBITRARY_IQ_CTL_read)(void);
83 u32 (*TX_INTF_REG_TX_CONFIG_read)(void);
84 u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
85 u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
86 u32 (*TX_INTF_REG_S_AXIS_FIFO_TH_read)(void);
87 u32 (*TX_INTF_REG_TX_HOLD_THRESHOLD_read)(void);
88 u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
89 u32 (*TX_INTF_REG_AMPDU_ACTION_CONFIG_read)(void);
90 u32 (*TX_INTF_REG_BB_GAIN_read)(void);
91 u32 (*TX_INTF_REG_ANT_SEL_read)(void);
92 u32 (*TX_INTF_REG_PHY_HDR_CONFIG_read)(void);
93 u32 (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read)(void);
94 u32 (*TX_INTF_REG_PKT_INFO1_read)(void);
95 u32 (*TX_INTF_REG_PKT_INFO2_read)(void);
96 u32 (*TX_INTF_REG_PKT_INFO3_read)(void);
97 u32 (*TX_INTF_REG_PKT_INFO4_read)(void);
98 u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
100 void (*TX_INTF_REG_MULTI_RST_write)(u32 value);
101 void (*TX_INTF_REG_ARBITRARY_IQ_write)(u32 value);
102 void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
103 void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
104 void (*TX_INTF_REG_CSI_FUZZER_write)(u32 value);
105 void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
106 void (*TX_INTF_REG_ARBITRARY_IQ_CTL_write)(u32 value);
107 void (*TX_INTF_REG_TX_CONFIG_write)(u32 value);
108 void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
109 void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
110 void (*TX_INTF_REG_S_AXIS_FIFO_TH_write)(u32 value);
111 void (*TX_INTF_REG_TX_HOLD_THRESHOLD_write)(u32 value);
112 void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
113 void (*TX_INTF_REG_AMPDU_ACTION_CONFIG_write)(u32 value);
114 void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
115 void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
116 void (*TX_INTF_REG_PHY_HDR_CONFIG_write)(u32 value);
117 void (*TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_write)(u32 value);
118 void (*TX_INTF_REG_PKT_INFO1_write)(u32 value);
119 void (*TX_INTF_REG_PKT_INFO2_write)(u32 value);
120 void (*TX_INTF_REG_PKT_INFO3_write)(u32 value);
121 void (*TX_INTF_REG_PKT_INFO4_write)(u32 value);