Lines Matching defs:rx_intf_driver_api

160 struct rx_intf_driver_api {  struct
161 	u32 io_start;
162 	u32 base_addr;
164 	u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
166 	u32 (*reg_read)(u32 reg);
167 	void (*reg_write)(u32 reg, u32 value);
169 	u32 (*RX_INTF_REG_MULTI_RST_read)(void);
170 	u32 (*RX_INTF_REG_MIXER_CFG_read)(void);
171 	u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);
172 	u32 (*RX_INTF_REG_IQ_CTRL_read)(void);
173 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
174 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);
175 	u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);
176 	u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
177 	u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
178 	u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
179 	u32 (*RX_INTF_REG_ANT_SEL_read)(void);
180 	u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);
181 	void (*RX_INTF_REG_MULTI_RST_write)(u32 value);
182 	void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);
183 	void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
184 	void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);
185 	void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
186 	void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);
187 	void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);
188 	void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
189 	void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
190 	void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
191 	void (*RX_INTF_REG_BB_GAIN_write)(u32 value);
192 	void (*RX_INTF_REG_ANT_SEL_write)(u32 value);
193 	void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);
195 	void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);
196 	void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);
197 	void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);