Lines Matching full:bits
144 * Bits 18 - 20 of the FPU Status Register will be read as 0,
176 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
185 * R4x00 interrupt enable / cause bits
197 * R4x00 interrupt cause bits
240 /* bits 6 & 7 are reserved on R[23]000 */
246 * Bits specific to the R4640/R4650
291 * Status register bits available in all MIPS CPUs.
372 * Bits in the coprocessor 0 config register.
374 /* Generic bits. */
386 /* Bits common to various processors. */
401 /* Bits specific to the R4xx0. */
406 /* Bits specific to the R5000. */
410 /* Bits specific to the RM7000. */
418 /* Bits specific to the R10000. */
431 /* Bits specific to the VR41xx. */
436 /* Bits specific to the R30xx. */
447 /* Bits specific to the TX49. */
453 /* Bits specific to the MIPS32/64 PRA. */
460 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
496 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.