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98 #define REG_T0 8 /* caller saved 0 …
114 #define REG_T8 24 /* caller saved 8 …
120 #define REG_S8 30 /* callee saved 8 …
121 #define REG_FP REG_S8 /* callee saved 8 …
148 #define FP32CTX_2 (FP32CTX_0 + (1 * 8))
149 #define FP32CTX_4 (FP32CTX_0 + (2 * 8))
150 #define FP32CTX_6 (FP32CTX_0 + (3 * 8))
151 #define FP32CTX_8 (FP32CTX_0 + (4 * 8))
152 #define FP32CTX_10 (FP32CTX_0 + (5 * 8))
153 #define FP32CTX_12 (FP32CTX_0 + (6 * 8))
154 #define FP32CTX_14 (FP32CTX_0 + (7 * 8))
155 #define FP32CTX_16 (FP32CTX_0 + (8 * 8))
156 #define FP32CTX_18 (FP32CTX_0 + (9 * 8))
157 #define FP32CTX_20 (FP32CTX_0 + (10 * 8))
158 #define FP32CTX_22 (FP32CTX_0 + (11 * 8))
159 #define FP32CTX_24 (FP32CTX_0 + (12 * 8))
160 #define FP32CTX_26 (FP32CTX_0 + (13 * 8))
161 #define FP32CTX_28 (FP32CTX_0 + (14 * 8))
162 #define FP32CTX_30 (FP32CTX_0 + (15 * 8))
163 #define FP32CTX_SIZE (FP32CTX_30 + (17 * 8))
166 #define FP64CTX_2 (FP64CTX_0 + (1 * 8))
167 #define FP64CTX_4 (FP64CTX_0 + (2 * 8))
168 #define FP64CTX_6 (FP64CTX_0 + (3 * 8))
169 #define FP64CTX_8 (FP64CTX_0 + (4 * 8))
170 #define FP64CTX_10 (FP64CTX_0 + (5 * 8))
171 #define FP64CTX_12 (FP64CTX_0 + (6 * 8))
172 #define FP64CTX_14 (FP64CTX_0 + (7 * 8))
173 #define FP64CTX_16 (FP64CTX_0 + (8 * 8))
174 #define FP64CTX_18 (FP64CTX_0 + (9 * 8))
175 #define FP64CTX_20 (FP64CTX_0 + (10 * 8))
176 #define FP64CTX_22 (FP64CTX_0 + (11 * 8))
177 #define FP64CTX_24 (FP64CTX_0 + (12 * 8))
178 #define FP64CTX_26 (FP64CTX_0 + (13 * 8))
179 #define FP64CTX_28 (FP64CTX_0 + (14 * 8))
180 #define FP64CTX_30 (FP64CTX_0 + (15 * 8))
181 #define FP64CTX_1 (FP64CTX_30 + (1 * 8))
182 #define FP64CTX_3 (FP64CTX_30 + (2 * 8))
183 #define FP64CTX_5 (FP64CTX_30 + (3 * 8))
184 #define FP64CTX_7 (FP64CTX_30 + (4 * 8))
185 #define FP64CTX_9 (FP64CTX_30 + (5 * 8))
186 #define FP64CTX_11 (FP64CTX_30 + (6 * 8))
187 #define FP64CTX_13 (FP64CTX_30 + (7 * 8))
188 #define FP64CTX_15 (FP64CTX_30 + (8 * 8))
189 #define FP64CTX_17 (FP64CTX_30 + (9 * 8))
190 #define FP64CTX_19 (FP64CTX_30 + (10 * 8))
191 #define FP64CTX_21 (FP64CTX_30 + (11 * 8))
192 #define FP64CTX_23 (FP64CTX_30 + (12 * 8))
193 #define FP64CTX_25 (FP64CTX_30 + (13 * 8))
194 #define FP64CTX_27 (FP64CTX_30 + (14 * 8))
195 #define FP64CTX_29 (FP64CTX_30 + (15 * 8))
196 #define FP64CTX_31 (FP64CTX_30 + (16 * 8))
197 #define FP64CTX_SIZE (FP64CTX_31 + (17 * 8))
233 #define CP0_BADVADDR $8
385 #define IE_SW0 (_ULCAST_(1) << 8)
397 #define C_SW0 (_ULCAST_(1) << 8)
480 #define STATUSB_IP0 8
481 #define STATUSF_IP0 (_ULCAST_(1) << 8)
533 #define CAUSEB_IP 8
534 #define CAUSEF_IP (_ULCAST_(255) << 8)
535 #define CAUSEB_IP0 8
536 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
657 #define CE0_CORRECTED_ECC_ERRORS 8
677 #define CE1_BRANCH_MISSPREDICTED 8
689 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
919 * The WatchLo register. There may be upto 8 of them.
939 * The WatchHi register. There may be upto 8 of them.