Lines Matching full:initial

56 #define DISRC0     (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
57 #define DISRCC0    (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
58 #define DIDST0     (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
59 #define DIDSTC0    (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
66 #define DISRC1     (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
67 #define DISRCC1    (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
68 #define DIDST1     (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
69 #define DIDSTC1    (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
76 #define DISRC2     (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
77 #define DISRCC2    (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
78 #define DIDST2     (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
79 #define DIDSTC2    (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
86 #define DISRC3     (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
87 #define DISRCC3    (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
88 #define DIDST3     (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
89 #define DIDSTC3    (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control