Lines Matching +full:0 +full:x01
21 // - Register address (bits 0-4)
24 #define ADDR_MASK 0x1F
25 #define BANK_MASK 0x60
26 #define SPRD_MASK 0x80
28 #define EIE 0x1B
29 #define EIR 0x1C
30 #define ESTAT 0x1D
31 #define ECON2 0x1E
32 #define ECON1 0x1F
33 // Bank 0 registers
34 #define ERDPTL (0x00|0x00)
35 #define ERDPTH (0x01|0x00)
36 #define EWRPTL (0x02|0x00)
37 #define EWRPTH (0x03|0x00)
38 #define ETXSTL (0x04|0x00)
39 #define ETXSTH (0x05|0x00)
40 #define ETXNDL (0x06|0x00)
41 #define ETXNDH (0x07|0x00)
42 #define ERXSTL (0x08|0x00)
43 #define ERXSTH (0x09|0x00)
44 #define ERXNDL (0x0A|0x00)
45 #define ERXNDH (0x0B|0x00)
46 #define ERXRDPTL (0x0C|0x00)
47 #define ERXRDPTH (0x0D|0x00)
48 #define ERXWRPTL (0x0E|0x00)
49 #define ERXWRPTH (0x0F|0x00)
50 #define EDMASTL (0x10|0x00)
51 #define EDMASTH (0x11|0x00)
52 #define EDMANDL (0x12|0x00)
53 #define EDMANDH (0x13|0x00)
54 #define EDMADSTL (0x14|0x00)
55 #define EDMADSTH (0x15|0x00)
56 #define EDMACSL (0x16|0x00)
57 #define EDMACSH (0x17|0x00)
59 #define EHT0 (0x00|0x20)
60 #define EHT1 (0x01|0x20)
61 #define EHT2 (0x02|0x20)
62 #define EHT3 (0x03|0x20)
63 #define EHT4 (0x04|0x20)
64 #define EHT5 (0x05|0x20)
65 #define EHT6 (0x06|0x20)
66 #define EHT7 (0x07|0x20)
67 #define EPMM0 (0x08|0x20)
68 #define EPMM1 (0x09|0x20)
69 #define EPMM2 (0x0A|0x20)
70 #define EPMM3 (0x0B|0x20)
71 #define EPMM4 (0x0C|0x20)
72 #define EPMM5 (0x0D|0x20)
73 #define EPMM6 (0x0E|0x20)
74 #define EPMM7 (0x0F|0x20)
75 #define EPMCSL (0x10|0x20)
76 #define EPMCSH (0x11|0x20)
77 #define EPMOL (0x14|0x20)
78 #define EPMOH (0x15|0x20)
79 #define EWOLIE (0x16|0x20)
80 #define EWOLIR (0x17|0x20)
81 #define ERXFCON (0x18|0x20)
82 #define EPKTCNT (0x19|0x20)
84 #define MACON1 (0x00|0x40|0x80)
85 #define MACON2 (0x01|0x40|0x80)
86 #define MACON3 (0x02|0x40|0x80)
87 #define MACON4 (0x03|0x40|0x80)
88 #define MABBIPG (0x04|0x40|0x80)
89 #define MAIPGL (0x06|0x40|0x80)
90 #define MAIPGH (0x07|0x40|0x80)
91 #define MACLCON1 (0x08|0x40|0x80)
92 #define MACLCON2 (0x09|0x40|0x80)
93 #define MAMXFLL (0x0A|0x40|0x80)
94 #define MAMXFLH (0x0B|0x40|0x80)
95 #define MAPHSUP (0x0D|0x40|0x80)
96 #define MICON (0x11|0x40|0x80)
97 #define MICMD (0x12|0x40|0x80)
98 #define MIREGADR (0x14|0x40|0x80)
99 #define MIWRL (0x16|0x40|0x80)
100 #define MIWRH (0x17|0x40|0x80)
101 #define MIRDL (0x18|0x40|0x80)
102 #define MIRDH (0x19|0x40|0x80)
104 #define MAADR1 (0x00|0x60|0x80)
105 #define MAADR0 (0x01|0x60|0x80)
106 #define MAADR3 (0x02|0x60|0x80)
107 #define MAADR2 (0x03|0x60|0x80)
108 #define MAADR5 (0x04|0x60|0x80)
109 #define MAADR4 (0x05|0x60|0x80)
110 #define EBSTSD (0x06|0x60)
111 #define EBSTCON (0x07|0x60)
112 #define EBSTCSL (0x08|0x60)
113 #define EBSTCSH (0x09|0x60)
114 #define MISTAT (0x0A|0x60|0x80)
115 #define EREVID (0x12|0x60)
116 #define ECOCON (0x15|0x60)
117 #define EFLOCON (0x17|0x60)
118 #define EPAUSL (0x18|0x60)
119 #define EPAUSH (0x19|0x60)
121 #define PHCON1 0x00
122 #define PHSTAT1 0x01
123 #define PHHID1 0x02
124 #define PHHID2 0x03
125 #define PHCON2 0x10
126 #define PHSTAT2 0x11
127 #define PHIE 0x12
128 #define PHIR 0x13
129 #define PHLCON 0x14
132 #define ERXFCON_UCEN 0x80
133 #define ERXFCON_ANDOR 0x40
134 #define ERXFCON_CRCEN 0x20
135 #define ERXFCON_PMEN 0x10
136 #define ERXFCON_MPEN 0x08
137 #define ERXFCON_HTEN 0x04
138 #define ERXFCON_MCEN 0x02
139 #define ERXFCON_BCEN 0x01
141 #define EIE_INTIE 0x80
142 #define EIE_PKTIE 0x40
143 #define EIE_DMAIE 0x20
144 #define EIE_LINKIE 0x10
145 #define EIE_TXIE 0x08
146 #define EIE_WOLIE 0x04
147 #define EIE_TXERIE 0x02
148 #define EIE_RXERIE 0x01
150 #define EIR_PKTIF 0x40
151 #define EIR_DMAIF 0x20
152 #define EIR_LINKIF 0x10
153 #define EIR_TXIF 0x08
154 #define EIR_WOLIF 0x04
155 #define EIR_TXERIF 0x02
156 #define EIR_RXERIF 0x01
158 #define ESTAT_INT 0x80
159 #define ESTAT_LATECOL 0x10
160 #define ESTAT_RXBUSY 0x04
161 #define ESTAT_TXABRT 0x02
162 #define ESTAT_CLKRDY 0x01
164 #define ECON2_AUTOINC 0x80
165 #define ECON2_PKTDEC 0x40
166 #define ECON2_PWRSV 0x20
167 #define ECON2_VRPS 0x08
169 #define ECON1_TXRST 0x80
170 #define ECON1_RXRST 0x40
171 #define ECON1_DMAST 0x20
172 #define ECON1_CSUMEN 0x10
173 #define ECON1_TXRTS 0x08
174 #define ECON1_RXEN 0x04
175 #define ECON1_BSEL1 0x02
176 #define ECON1_BSEL0 0x01
178 #define MACON1_LOOPBK 0x10
179 #define MACON1_TXPAUS 0x08
180 #define MACON1_RXPAUS 0x04
181 #define MACON1_PASSALL 0x02
182 #define MACON1_MARXEN 0x01
184 #define MACON2_MARST 0x80
185 #define MACON2_RNDRST 0x40
186 #define MACON2_MARXRST 0x08
187 #define MACON2_RFUNRST 0x04
188 #define MACON2_MATXRST 0x02
189 #define MACON2_TFUNRST 0x01
191 #define MACON3_PADCFG2 0x80
192 #define MACON3_PADCFG1 0x40
193 #define MACON3_PADCFG0 0x20
194 #define MACON3_TXCRCEN 0x10
195 #define MACON3_PHDRLEN 0x08
196 #define MACON3_HFRMLEN 0x04
197 #define MACON3_FRMLNEN 0x02
198 #define MACON3_FULDPX 0x01
204 #define MICMD_MIISCAN 0x02
205 #define MICMD_MIIRD 0x01
207 #define MISTAT_NVALID 0x04
208 #define MISTAT_SCAN 0x02
209 #define MISTAT_BUSY 0x01
211 #define PHCON1_PRST 0x8000
212 #define PHCON1_PLOOPBK 0x4000
213 #define PHCON1_PPWRSV 0x0800
214 #define PHCON1_PDPXMD 0x0100
216 #define PHSTAT1_PFDPX 0x1000
217 #define PHSTAT1_PHDPX 0x0800
218 #define PHSTAT1_LLSTAT 0x0004
219 #define PHSTAT1_JBSTAT 0x0002
228 #define PHCON2_FRCLINK 0x4000
229 #define PHCON2_TXDIS 0x2000
230 #define PHCON2_JABBER 0x0400
231 #define PHCON2_HDLDIS 0x0100
240 #define PKTCTRL_PHUGEEN 0x08
241 #define PKTCTRL_PPADEN 0x04
242 #define PKTCTRL_PCRCEN 0x02
243 #define PKTCTRL_POVERRIDE 0x01
246 #define TSV_TXBYTECNT 0
269 #define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
288 #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
291 #define ENC28J60_READ_CTRL_REG 0x00
292 #define ENC28J60_READ_BUF_MEM 0x3A
293 #define ENC28J60_WRITE_CTRL_REG 0x40
294 #define ENC28J60_WRITE_BUF_MEM 0x7A
295 #define ENC28J60_BIT_FIELD_SET 0x80
296 #define ENC28J60_BIT_FIELD_CLR 0xA0
297 #define ENC28J60_SOFT_RESET 0xFF
306 // start with recbuf at 0/
307 #define RXSTART_INIT 0x0
309 #define RXSTOP_INIT (0x1FFF - MAX_TX_PACKAGE_SIZE*2) - 1
310 // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
312 #define TXSTART_INIT (0x1FFF - MAX_TX_PACKAGE_SIZE*2)
314 #define TXSTOP_INIT 0x1FFF