Lines Matching +full:rs485 +full:- +full:rts +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
14 * not have an RI input, nor do they have DTR or RTS outputs. If
35 #include <linux/dma-mapping.h>
37 #include <linux/delay.h>
82 /* The size of the array - must be last */
268 unsigned int fifosize; /* vendor-specific */
269 unsigned int fixed_baud; /* vendor-set fixed baud rate */
291 return uap->reg_offset[reg]; in pl011_reg_to_offset()
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
299 return (uap->port.iotype == UPIO_MEM32) ? in pl011_read()
306 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_write()
308 if (uap->port.iotype == UPIO_MEM32) in pl011_write()
334 uap->port.icount.rx++; in pl011_fifo_to_tty()
339 uap->port.icount.brk++; in pl011_fifo_to_tty()
340 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
343 uap->port.icount.parity++; in pl011_fifo_to_tty()
345 uap->port.icount.frame++; in pl011_fifo_to_tty()
348 uap->port.icount.overrun++; in pl011_fifo_to_tty()
350 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
360 sysrq = uart_prepare_sysrq_char(&uap->port, ch & 255); in pl011_fifo_to_tty()
362 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
380 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, in pl011_dmabuf_init()
381 &db->dma, GFP_KERNEL); in pl011_dmabuf_init()
382 if (!db->buf) in pl011_dmabuf_init()
383 return -ENOMEM; in pl011_dmabuf_init()
384 db->len = PL011_DMA_BUFFER_SIZE; in pl011_dmabuf_init()
392 if (db->buf) { in pl011_dmabuf_free()
393 dma_free_coherent(chan->device->dev, in pl011_dmabuf_free()
394 PL011_DMA_BUFFER_SIZE, db->buf, db->dma); in pl011_dmabuf_free()
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
402 struct device *dev = uap->port.dev; in pl011_dma_probe()
404 .dst_addr = uap->port.mapbase + in pl011_dma_probe()
408 .dst_maxburst = uap->fifosize >> 1, in pl011_dma_probe()
414 uap->dma_probed = true; in pl011_dma_probe()
417 if (PTR_ERR(chan) == -EPROBE_DEFER) { in pl011_dma_probe()
418 uap->dma_probed = false; in pl011_dma_probe()
423 if (!plat || !plat->dma_filter) { in pl011_dma_probe()
424 dev_dbg(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
432 chan = dma_request_channel(mask, plat->dma_filter, in pl011_dma_probe()
433 plat->dma_tx_param); in pl011_dma_probe()
435 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
441 uap->dmatx.chan = chan; in pl011_dma_probe()
443 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
444 dma_chan_name(uap->dmatx.chan)); in pl011_dma_probe()
449 if (IS_ERR(chan) && plat && plat->dma_rx_param) { in pl011_dma_probe()
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); in pl011_dma_probe()
453 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
460 .src_addr = uap->port.mapbase + in pl011_dma_probe()
464 .src_maxburst = uap->fifosize >> 2, in pl011_dma_probe()
478 dev_info(uap->port.dev, in pl011_dma_probe()
479 "RX DMA disabled - no residue processing\n"); in pl011_dma_probe()
484 uap->dmarx.chan = chan; in pl011_dma_probe()
486 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
487 if (plat && plat->dma_rx_poll_enable) { in pl011_dma_probe()
489 if (plat->dma_rx_poll_rate) { in pl011_dma_probe()
490 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; in pl011_dma_probe()
498 uap->dmarx.auto_poll_rate = true; in pl011_dma_probe()
499 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
502 if (plat->dma_rx_poll_timeout) in pl011_dma_probe()
503 uap->dmarx.poll_timeout = in pl011_dma_probe()
504 plat->dma_rx_poll_timeout; in pl011_dma_probe()
506 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
507 } else if (!plat && dev->of_node) { in pl011_dma_probe()
508 uap->dmarx.auto_poll_rate = in pl011_dma_probe()
509 of_property_read_bool(dev->of_node, "auto-poll"); in pl011_dma_probe()
510 if (uap->dmarx.auto_poll_rate) { in pl011_dma_probe()
513 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0) in pl011_dma_probe()
514 uap->dmarx.poll_rate = x; in pl011_dma_probe()
516 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
517 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0) in pl011_dma_probe()
518 uap->dmarx.poll_timeout = x; in pl011_dma_probe()
520 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
523 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
524 dma_chan_name(uap->dmarx.chan)); in pl011_dma_probe()
530 if (uap->dmatx.chan) in pl011_dma_remove()
531 dma_release_channel(uap->dmatx.chan); in pl011_dma_remove()
532 if (uap->dmarx.chan) in pl011_dma_remove()
533 dma_release_channel(uap->dmarx.chan); in pl011_dma_remove()
547 struct tty_port *tport = &uap->port.state->port; in pl011_dma_tx_callback()
548 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_callback()
552 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_tx_callback()
553 if (uap->dmatx.queued) in pl011_dma_tx_callback()
554 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, in pl011_dma_tx_callback()
555 dmatx->len, DMA_TO_DEVICE); in pl011_dma_tx_callback()
557 dmacr = uap->dmacr; in pl011_dma_tx_callback()
558 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
559 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
563 * some reason (eg, XOFF received, or we want to send an X-char.) in pl011_dma_tx_callback()
566 * and the rest of the driver - if the driver disables TX DMA while in pl011_dma_tx_callback()
570 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
571 kfifo_is_empty(&tport->xmit_fifo)) { in pl011_dma_tx_callback()
572 uap->dmatx.queued = false; in pl011_dma_tx_callback()
573 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
580 * have data pending to be sent. Re-enable the TX IRQ. in pl011_dma_tx_callback()
584 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
597 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_refill()
598 struct dma_chan *chan = dmatx->chan; in pl011_dma_tx_refill()
599 struct dma_device *dma_dev = chan->device; in pl011_dma_tx_refill()
601 struct tty_port *tport = &uap->port.state->port; in pl011_dma_tx_refill()
610 count = kfifo_len(&tport->xmit_fifo); in pl011_dma_tx_refill()
611 if (count < (uap->fifosize >> 1)) { in pl011_dma_tx_refill()
612 uap->dmatx.queued = false; in pl011_dma_tx_refill()
620 count -= 1; in pl011_dma_tx_refill()
626 count = kfifo_out_peek(&tport->xmit_fifo, dmatx->buf, count); in pl011_dma_tx_refill()
627 dmatx->len = count; in pl011_dma_tx_refill()
628 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, in pl011_dma_tx_refill()
630 if (dmatx->dma == DMA_MAPPING_ERROR) { in pl011_dma_tx_refill()
631 uap->dmatx.queued = false; in pl011_dma_tx_refill()
632 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
633 return -EBUSY; in pl011_dma_tx_refill()
636 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, in pl011_dma_tx_refill()
639 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); in pl011_dma_tx_refill()
640 uap->dmatx.queued = false; in pl011_dma_tx_refill()
645 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
646 return -EBUSY; in pl011_dma_tx_refill()
650 desc->callback = pl011_dma_tx_callback; in pl011_dma_tx_refill()
651 desc->callback_param = uap; in pl011_dma_tx_refill()
657 dma_dev->device_issue_pending(chan); in pl011_dma_tx_refill()
659 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
660 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
661 uap->dmatx.queued = true; in pl011_dma_tx_refill()
667 uart_xmit_advance(&uap->port, count); in pl011_dma_tx_refill()
669 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in pl011_dma_tx_refill()
670 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
676 * We received a transmit interrupt without a pending X-char but with
685 if (!uap->using_tx_dma) in pl011_dma_tx_irq()
690 * TX interrupt, it will be because we've just sent an X-char. in pl011_dma_tx_irq()
693 if (uap->dmatx.queued) { in pl011_dma_tx_irq()
694 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
695 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_irq()
696 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
697 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
706 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
707 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
719 if (uap->dmatx.queued) { in pl011_dma_tx_stop()
720 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_stop()
721 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_stop()
737 if (!uap->using_tx_dma) in pl011_dma_tx_start()
740 if (!uap->port.x_char) { in pl011_dma_tx_start()
741 /* no X-char, try to push chars out in DMA mode */ in pl011_dma_tx_start()
744 if (!uap->dmatx.queued) { in pl011_dma_tx_start()
746 uap->im &= ~UART011_TXIM; in pl011_dma_tx_start()
747 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_start()
751 } else if (!(uap->dmacr & UART011_TXDMAE)) { in pl011_dma_tx_start()
752 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_start()
753 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
759 * We have an X-char to send. Disable DMA to prevent it loading in pl011_dma_tx_start()
762 dmacr = uap->dmacr; in pl011_dma_tx_start()
763 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
764 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
770 * loaded the character, we should just re-enable DMA. in pl011_dma_tx_start()
775 pl011_write(uap->port.x_char, uap, REG_DR); in pl011_dma_tx_start()
776 uap->port.icount.tx++; in pl011_dma_tx_start()
777 uap->port.x_char = 0; in pl011_dma_tx_start()
779 /* Success - restore the DMA state */ in pl011_dma_tx_start()
780 uap->dmacr = dmacr; in pl011_dma_tx_start()
791 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
792 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
797 if (!uap->using_tx_dma) in pl011_dma_flush_buffer()
800 dmaengine_terminate_async(uap->dmatx.chan); in pl011_dma_flush_buffer()
802 if (uap->dmatx.queued) { in pl011_dma_flush_buffer()
803 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, in pl011_dma_flush_buffer()
804 uap->dmatx.len, DMA_TO_DEVICE); in pl011_dma_flush_buffer()
805 uap->dmatx.queued = false; in pl011_dma_flush_buffer()
806 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_flush_buffer()
807 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_flush_buffer()
815 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_trigger_dma()
816 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_trigger_dma()
821 return -EIO; in pl011_dma_rx_trigger_dma()
824 dbuf = uap->dmarx.use_buf_b ? in pl011_dma_rx_trigger_dma()
825 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_trigger_dma()
826 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, in pl011_dma_rx_trigger_dma()
835 uap->dmarx.running = false; in pl011_dma_rx_trigger_dma()
837 return -EBUSY; in pl011_dma_rx_trigger_dma()
841 desc->callback = pl011_dma_rx_callback; in pl011_dma_rx_trigger_dma()
842 desc->callback_param = uap; in pl011_dma_rx_trigger_dma()
843 dmarx->cookie = dmaengine_submit(desc); in pl011_dma_rx_trigger_dma()
846 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
847 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_trigger_dma()
848 uap->dmarx.running = true; in pl011_dma_rx_trigger_dma()
850 uap->im &= ~UART011_RXIM; in pl011_dma_rx_trigger_dma()
851 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_trigger_dma()
859 * with the port spinlock uap->port.lock held.
865 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars()
867 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_chars()
871 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_chars()
874 if (uap->dmarx.poll_rate) { in pl011_dma_rx_chars()
876 dmataken = dbuf->len - dmarx->last_residue; in pl011_dma_rx_chars()
879 pending -= dmataken; in pl011_dma_rx_chars()
889 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending); in pl011_dma_rx_chars()
891 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
893 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
898 if (uap->dmarx.poll_rate) in pl011_dma_rx_chars()
899 dmarx->last_residue = dbuf->len; in pl011_dma_rx_chars()
924 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
932 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_irq()
933 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_irq()
934 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? in pl011_dma_rx_irq()
935 &dmarx->dbuf_b : &dmarx->dbuf_a; in pl011_dma_rx_irq()
946 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
947 dmastat = rxchan->device->device_tx_status(rxchan, in pl011_dma_rx_irq()
948 dmarx->cookie, &state); in pl011_dma_rx_irq()
950 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
952 /* Disable RX DMA - incoming data will wait in the FIFO */ in pl011_dma_rx_irq()
953 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_irq()
954 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_irq()
955 uap->dmarx.running = false; in pl011_dma_rx_irq()
957 pending = dbuf->len - state.residue; in pl011_dma_rx_irq()
959 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_irq()
966 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); in pl011_dma_rx_irq()
968 /* Switch buffer & re-trigger DMA job */ in pl011_dma_rx_irq()
969 dmarx->use_buf_b = !dmarx->use_buf_b; in pl011_dma_rx_irq()
971 dev_dbg(uap->port.dev, in pl011_dma_rx_irq()
973 uap->im |= UART011_RXIM; in pl011_dma_rx_irq()
974 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_irq()
981 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_callback()
982 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_callback()
983 bool lastbuf = dmarx->use_buf_b; in pl011_dma_rx_callback()
984 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? in pl011_dma_rx_callback()
985 &dmarx->dbuf_b : &dmarx->dbuf_a; in pl011_dma_rx_callback()
997 uart_port_lock_irq(&uap->port); in pl011_dma_rx_callback()
1002 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_callback()
1003 pending = dbuf->len - state.residue; in pl011_dma_rx_callback()
1005 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_callback()
1008 uap->dmarx.running = false; in pl011_dma_rx_callback()
1009 dmarx->use_buf_b = !lastbuf; in pl011_dma_rx_callback()
1013 uart_unlock_and_check_sysrq(&uap->port); in pl011_dma_rx_callback()
1019 dev_dbg(uap->port.dev, in pl011_dma_rx_callback()
1021 uap->im |= UART011_RXIM; in pl011_dma_rx_callback()
1022 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_callback()
1033 if (!uap->using_rx_dma) in pl011_dma_rx_stop()
1037 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_stop()
1038 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_stop()
1049 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll()
1050 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_poll()
1051 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_poll()
1059 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_poll()
1060 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_poll()
1061 if (likely(state.residue < dmarx->last_residue)) { in pl011_dma_rx_poll()
1062 dmataken = dbuf->len - dmarx->last_residue; in pl011_dma_rx_poll()
1063 size = dmarx->last_residue - state.residue; in pl011_dma_rx_poll()
1064 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, in pl011_dma_rx_poll()
1067 dmarx->last_residue = state.residue; in pl011_dma_rx_poll()
1068 dmarx->last_jiffies = jiffies; in pl011_dma_rx_poll()
1076 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) in pl011_dma_rx_poll()
1077 > uap->dmarx.poll_timeout) { in pl011_dma_rx_poll()
1078 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_rx_poll()
1080 uap->im |= UART011_RXIM; in pl011_dma_rx_poll()
1081 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_poll()
1082 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_rx_poll()
1084 uap->dmarx.running = false; in pl011_dma_rx_poll()
1086 del_timer(&uap->dmarx.timer); in pl011_dma_rx_poll()
1088 mod_timer(&uap->dmarx.timer, in pl011_dma_rx_poll()
1089 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_rx_poll()
1097 if (!uap->dma_probed) in pl011_dma_startup()
1100 if (!uap->dmatx.chan) in pl011_dma_startup()
1103 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); in pl011_dma_startup()
1104 if (!uap->dmatx.buf) { in pl011_dma_startup()
1105 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1109 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1112 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1113 uap->using_tx_dma = true; in pl011_dma_startup()
1115 if (!uap->dmarx.chan) in pl011_dma_startup()
1119 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1122 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1127 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, in pl011_dma_startup()
1130 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1132 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1137 uap->using_rx_dma = true; in pl011_dma_startup()
1141 uap->dmacr |= UART011_DMAONERR; in pl011_dma_startup()
1142 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_startup()
1149 if (uap->vendor->dma_threshold) in pl011_dma_startup()
1153 if (uap->using_rx_dma) { in pl011_dma_startup()
1155 dev_dbg(uap->port.dev, in pl011_dma_startup()
1157 if (uap->dmarx.poll_rate) { in pl011_dma_startup()
1158 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); in pl011_dma_startup()
1159 mod_timer(&uap->dmarx.timer, in pl011_dma_startup()
1160 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_startup()
1161 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1162 uap->dmarx.last_jiffies = jiffies; in pl011_dma_startup()
1169 if (!(uap->using_tx_dma || uap->using_rx_dma)) in pl011_dma_shutdown()
1173 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) in pl011_dma_shutdown()
1176 uart_port_lock_irq(&uap->port); in pl011_dma_shutdown()
1177 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); in pl011_dma_shutdown()
1178 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_shutdown()
1179 uart_port_unlock_irq(&uap->port); in pl011_dma_shutdown()
1181 if (uap->using_tx_dma) { in pl011_dma_shutdown()
1183 dmaengine_terminate_all(uap->dmatx.chan); in pl011_dma_shutdown()
1184 if (uap->dmatx.queued) { in pl011_dma_shutdown()
1185 dma_unmap_single(uap->dmatx.chan->device->dev, in pl011_dma_shutdown()
1186 uap->dmatx.dma, uap->dmatx.len, in pl011_dma_shutdown()
1188 uap->dmatx.queued = false; in pl011_dma_shutdown()
1191 kfree(uap->dmatx.buf); in pl011_dma_shutdown()
1192 uap->using_tx_dma = false; in pl011_dma_shutdown()
1195 if (uap->using_rx_dma) { in pl011_dma_shutdown()
1196 dmaengine_terminate_all(uap->dmarx.chan); in pl011_dma_shutdown()
1198 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1199 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1200 if (uap->dmarx.poll_rate) in pl011_dma_shutdown()
1201 del_timer_sync(&uap->dmarx.timer); in pl011_dma_shutdown()
1202 uap->using_rx_dma = false; in pl011_dma_shutdown()
1208 return uap->using_rx_dma; in pl011_dma_rx_available()
1213 return uap->using_rx_dma && uap->dmarx.running; in pl011_dma_rx_running()
1254 return -EIO; in pl011_dma_rx_trigger_dma()
1272 struct uart_port *port = &uap->port; in pl011_rs485_tx_stop()
1275 if (uap->rs485_tx_state == SEND) in pl011_rs485_tx_stop()
1276 uap->rs485_tx_state = WAIT_AFTER_SEND; in pl011_rs485_tx_stop()
1278 if (uap->rs485_tx_state == WAIT_AFTER_SEND) { in pl011_rs485_tx_stop()
1281 hrtimer_start(&uap->trigger_stop_tx, in pl011_rs485_tx_stop()
1282 uap->rs485_tx_drain_interval, in pl011_rs485_tx_stop()
1286 if (port->rs485.delay_rts_after_send > 0) { in pl011_rs485_tx_stop()
1287 hrtimer_start(&uap->trigger_stop_tx, in pl011_rs485_tx_stop()
1288 ms_to_ktime(port->rs485.delay_rts_after_send), in pl011_rs485_tx_stop()
1292 /* Continue without any delay */ in pl011_rs485_tx_stop()
1293 } else if (uap->rs485_tx_state == WAIT_AFTER_RTS) { in pl011_rs485_tx_stop()
1294 hrtimer_try_to_cancel(&uap->trigger_start_tx); in pl011_rs485_tx_stop()
1299 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in pl011_rs485_tx_stop()
1309 uap->rs485_tx_state = OFF; in pl011_rs485_tx_stop()
1317 if (port->rs485.flags & SER_RS485_ENABLED && in pl011_stop_tx()
1318 uap->rs485_tx_state == WAIT_AFTER_RTS) { in pl011_stop_tx()
1323 uap->im &= ~UART011_TXIM; in pl011_stop_tx()
1324 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_tx()
1327 if (port->rs485.flags & SER_RS485_ENABLED && in pl011_stop_tx()
1328 uap->rs485_tx_state != OFF) in pl011_stop_tx()
1338 uap->im |= UART011_TXIM; in pl011_start_tx_pio()
1339 pl011_write(uap->im, uap, REG_IMSC); in pl011_start_tx_pio()
1345 struct uart_port *port = &uap->port; in pl011_rs485_tx_start()
1348 if (uap->rs485_tx_state == WAIT_AFTER_RTS) { in pl011_rs485_tx_start()
1349 uap->rs485_tx_state = SEND; in pl011_rs485_tx_start()
1352 if (uap->rs485_tx_state == WAIT_AFTER_SEND) { in pl011_rs485_tx_start()
1353 hrtimer_try_to_cancel(&uap->trigger_stop_tx); in pl011_rs485_tx_start()
1354 uap->rs485_tx_state = SEND; in pl011_rs485_tx_start()
1357 /* uap->rs485_tx_state == OFF */ in pl011_rs485_tx_start()
1361 /* Disable receiver if half-duplex */ in pl011_rs485_tx_start()
1362 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in pl011_rs485_tx_start()
1365 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in pl011_rs485_tx_start()
1372 if (port->rs485.delay_rts_before_send > 0) { in pl011_rs485_tx_start()
1373 uap->rs485_tx_state = WAIT_AFTER_RTS; in pl011_rs485_tx_start()
1374 hrtimer_start(&uap->trigger_start_tx, in pl011_rs485_tx_start()
1375 ms_to_ktime(port->rs485.delay_rts_before_send), in pl011_rs485_tx_start()
1378 uap->rs485_tx_state = SEND; in pl011_rs485_tx_start()
1387 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && in pl011_start_tx()
1388 uap->rs485_tx_state != SEND) { in pl011_start_tx()
1390 if (uap->rs485_tx_state == WAIT_AFTER_RTS) in pl011_start_tx()
1404 uart_port_lock_irqsave(&uap->port, &flags); in pl011_trigger_start_tx()
1405 if (uap->rs485_tx_state == WAIT_AFTER_RTS) in pl011_trigger_start_tx()
1406 pl011_start_tx(&uap->port); in pl011_trigger_start_tx()
1407 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_trigger_start_tx()
1418 uart_port_lock_irqsave(&uap->port, &flags); in pl011_trigger_stop_tx()
1419 if (uap->rs485_tx_state == WAIT_AFTER_SEND) in pl011_trigger_stop_tx()
1421 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_trigger_stop_tx()
1431 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM | in pl011_stop_rx()
1433 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_rx()
1452 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM; in pl011_enable_ms()
1453 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_ms()
1457 __releases(&uap->port.lock) in pl011_rx_chars()
1458 __acquires(&uap->port.lock) in pl011_rx_chars()
1462 uart_port_unlock(&uap->port); in pl011_rx_chars()
1463 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1470 dev_dbg(uap->port.dev, in pl011_rx_chars()
1472 uap->im |= UART011_RXIM; in pl011_rx_chars()
1473 pl011_write(uap->im, uap, REG_IMSC); in pl011_rx_chars()
1477 if (uap->dmarx.poll_rate) { in pl011_rx_chars()
1478 uap->dmarx.last_jiffies = jiffies; in pl011_rx_chars()
1479 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_rx_chars()
1480 mod_timer(&uap->dmarx.timer, in pl011_rx_chars()
1481 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_rx_chars()
1486 uart_port_lock(&uap->port); in pl011_rx_chars()
1497 uap->port.icount.tx++; in pl011_tx_char()
1505 struct tty_port *tport = &uap->port.state->port; in pl011_tx_chars()
1506 int count = uap->fifosize >> 1; in pl011_tx_chars()
1508 if (uap->port.x_char) { in pl011_tx_chars()
1509 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1511 uap->port.x_char = 0; in pl011_tx_chars()
1512 --count; in pl011_tx_chars()
1514 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1515 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1526 if (likely(from_irq) && count-- == 0) in pl011_tx_chars()
1529 if (!kfifo_peek(&tport->xmit_fifo, &c)) in pl011_tx_chars()
1535 kfifo_skip(&tport->xmit_fifo); in pl011_tx_chars()
1538 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in pl011_tx_chars()
1539 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1541 if (kfifo_is_empty(&tport->xmit_fifo)) { in pl011_tx_chars()
1542 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1554 delta = status ^ uap->old_status; in pl011_modem_status()
1555 uap->old_status = status; in pl011_modem_status()
1561 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1563 if (delta & uap->vendor->fr_dsr) in pl011_modem_status()
1564 uap->port.icount.dsr++; in pl011_modem_status()
1566 if (delta & uap->vendor->fr_cts) in pl011_modem_status()
1567 uart_handle_cts_change(&uap->port, in pl011_modem_status()
1568 status & uap->vendor->fr_cts); in pl011_modem_status()
1570 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1575 if (!uap->vendor->cts_event_workaround) in check_apply_cts_event_workaround()
1582 * WA: introduce 26ns(1 uart clk) delay before W1C; in check_apply_cts_event_workaround()
1583 * single apb access will incur 2 pclk(133.12Mhz) delay, in check_apply_cts_event_workaround()
1596 uart_port_lock(&uap->port); in pl011_int()
1597 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1617 if (pass_counter-- == 0) in pl011_int()
1620 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1625 uart_unlock_and_check_sysrq(&uap->port); in pl011_int()
1636 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; in pl011_tx_empty()
1638 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? in pl011_tx_empty()
1656 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR); in pl011_get_mctrl()
1657 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS); in pl011_get_mctrl()
1658 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG); in pl011_get_mctrl()
1685 if (port->status & UPSTAT_AUTORTS) { in pl011_set_mctrl()
1686 /* We need to disable auto-RTS if we want to turn RTS off */ in pl011_set_mctrl()
1700 uart_port_lock_irqsave(&uap->port, &flags); in pl011_break_ctl()
1702 if (break_state == -1) in pl011_break_ctl()
1707 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_break_ctl()
1774 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1779 retval = clk_prepare_enable(uap->clk); in pl011_hwinit()
1783 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1794 uap->im = pl011_read(uap, REG_IMSC); in pl011_hwinit()
1797 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1800 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1801 if (plat->init) in pl011_hwinit()
1802 plat->init(); in pl011_hwinit()
1820 * to get this delay write read only register 10 times in pl011_write_lcr_h()
1830 pl011_write(uap->im, uap, REG_IMSC); in pl011_allocate_irq()
1832 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); in pl011_allocate_irq()
1845 uart_port_lock_irqsave(&uap->port, &flags); in pl011_enable_interrupts()
1856 for (i = 0; i < uap->fifosize * 2; ++i) { in pl011_enable_interrupts()
1863 uap->im = UART011_RTIM; in pl011_enable_interrupts()
1865 uap->im |= UART011_RXIM; in pl011_enable_interrupts()
1866 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_interrupts()
1867 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_enable_interrupts()
1875 uart_port_lock_irqsave(&uap->port, &flags); in pl011_unthrottle_rx()
1877 uap->im = UART011_RTIM; in pl011_unthrottle_rx()
1879 uap->im |= UART011_RXIM; in pl011_unthrottle_rx()
1881 pl011_write(uap->im, uap, REG_IMSC); in pl011_unthrottle_rx()
1884 if (uap->using_rx_dma) { in pl011_unthrottle_rx()
1885 uap->dmacr |= UART011_RXDMAE; in pl011_unthrottle_rx()
1886 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_unthrottle_rx()
1890 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_unthrottle_rx()
1908 pl011_write(uap->vendor->ifls, uap, REG_IFLS); in pl011_startup()
1910 uart_port_lock_irq(&uap->port); in pl011_startup()
1916 if (!(port->rs485.flags & SER_RS485_ENABLED)) in pl011_startup()
1921 uart_port_unlock_irq(&uap->port); in pl011_startup()
1926 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1936 clk_disable_unprepare(uap->clk); in pl011_startup()
1955 uap->old_status = 0; in sbsa_uart_startup()
1972 * disable the port. It should not disable RTS and DTR.
1973 * Also RTS and DTR state should be preserved to restore
1980 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_disable_uart()
1981 uart_port_lock_irq(&uap->port); in pl011_disable_uart()
1986 uart_port_unlock_irq(&uap->port); in pl011_disable_uart()
1998 uart_port_lock_irq(&uap->port); in pl011_disable_interrupts()
2001 uap->im = 0; in pl011_disable_interrupts()
2002 pl011_write(uap->im, uap, REG_IMSC); in pl011_disable_interrupts()
2005 uart_port_unlock_irq(&uap->port); in pl011_disable_interrupts()
2017 if ((port->rs485.flags & SER_RS485_ENABLED && uap->rs485_tx_state != OFF)) in pl011_shutdown()
2020 free_irq(uap->port.irq, uap); in pl011_shutdown()
2027 clk_disable_unprepare(uap->clk); in pl011_shutdown()
2029 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
2031 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
2034 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
2035 if (plat->exit) in pl011_shutdown()
2036 plat->exit(); in pl011_shutdown()
2039 if (uap->port.ops->flush_buffer) in pl011_shutdown()
2040 uap->port.ops->flush_buffer(port); in pl011_shutdown()
2050 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
2052 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
2053 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
2059 port->read_status_mask = UART011_DR_OE | 255; in pl011_setup_status_masks()
2060 if (termios->c_iflag & INPCK) in pl011_setup_status_masks()
2061 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2062 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in pl011_setup_status_masks()
2063 port->read_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2068 port->ignore_status_mask = 0; in pl011_setup_status_masks()
2069 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2070 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2071 if (termios->c_iflag & IGNBRK) { in pl011_setup_status_masks()
2072 port->ignore_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2077 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2078 port->ignore_status_mask |= UART011_DR_OE; in pl011_setup_status_masks()
2084 if ((termios->c_cflag & CREAD) == 0) in pl011_setup_status_masks()
2085 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_setup_status_masks()
2099 if (uap->vendor->oversampling) in pl011_set_termios()
2108 port->uartclk / clkdiv); in pl011_set_termios()
2113 if (uap->dmarx.auto_poll_rate) in pl011_set_termios()
2114 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); in pl011_set_termios()
2117 if (baud > port->uartclk / 16) in pl011_set_termios()
2118 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
2120 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
2122 switch (termios->c_cflag & CSIZE) { in pl011_set_termios()
2136 if (termios->c_cflag & CSTOPB) in pl011_set_termios()
2138 if (termios->c_cflag & PARENB) { in pl011_set_termios()
2140 if (!(termios->c_cflag & PARODD)) in pl011_set_termios()
2142 if (termios->c_cflag & CMSPAR) in pl011_set_termios()
2145 if (uap->fifosize > 1) in pl011_set_termios()
2148 bits = tty_get_frame_size(termios->c_cflag); in pl011_set_termios()
2153 * Update the per-port timeout. in pl011_set_termios()
2155 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
2162 uap->rs485_tx_drain_interval = ns_to_ktime(DIV_ROUND_UP(bits * NSEC_PER_SEC, baud)); in pl011_set_termios()
2166 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
2169 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_set_termios()
2170 termios->c_cflag &= ~CRTSCTS; in pl011_set_termios()
2174 if (termios->c_cflag & CRTSCTS) { in pl011_set_termios()
2179 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in pl011_set_termios()
2182 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_set_termios()
2185 if (uap->vendor->oversampling) { in pl011_set_termios()
2186 if (baud > port->uartclk / 16) in pl011_set_termios()
2198 if (uap->vendor->oversampling) { in pl011_set_termios()
2200 quot -= 1; in pl011_set_termios()
2202 quot -= 2; in pl011_set_termios()
2209 * ----------v----------v----------v----------v----- in pl011_set_termios()
2212 * ----------^----------^----------^----------^----- in pl011_set_termios()
2235 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); in sbsa_uart_set_termios()
2238 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); in sbsa_uart_set_termios()
2239 termios->c_cflag &= ~(CMSPAR | CRTSCTS); in sbsa_uart_set_termios()
2240 termios->c_cflag |= CS8 | CLOCAL; in sbsa_uart_set_termios()
2243 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
2252 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
2261 port->type = PORT_AMBA; in pl011_config_port()
2271 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) in pl011_verify_port()
2272 ret = -EINVAL; in pl011_verify_port()
2273 if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs()) in pl011_verify_port()
2274 ret = -EINVAL; in pl011_verify_port()
2275 if (ser->baud_base < 9600) in pl011_verify_port()
2276 ret = -EINVAL; in pl011_verify_port()
2277 if (port->mapbase != (unsigned long)ser->iomem_base) in pl011_verify_port()
2278 ret = -EINVAL; in pl011_verify_port()
2283 struct serial_rs485 *rs485) in pl011_rs485_config() argument
2288 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_rs485_config()
2291 /* Make sure auto RTS is disabled */ in pl011_rs485_config()
2292 if (rs485->flags & SER_RS485_ENABLED) { in pl011_rs485_config()
2297 port->status &= ~UPSTAT_AUTORTS; in pl011_rs485_config()
2374 struct uart_amba_port *uap = amba_ports[co->index]; in pl011_console_write()
2379 clk_enable(uap->clk); in pl011_console_write()
2382 locked = uart_port_trylock_irqsave(&uap->port, &flags); in pl011_console_write()
2384 uart_port_lock_irqsave(&uap->port, &flags); in pl011_console_write()
2389 if (!uap->vendor->always_enabled) { in pl011_console_write()
2396 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2403 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) in pl011_console_write()
2404 & uap->vendor->fr_busy) in pl011_console_write()
2406 if (!uap->vendor->always_enabled) in pl011_console_write()
2410 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_console_write()
2412 clk_disable(uap->clk); in pl011_console_write()
2441 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2443 if (uap->vendor->oversampling && in pl011_console_get_options()
2462 if (co->index >= UART_NR) in pl011_console_setup()
2463 co->index = 0; in pl011_console_setup()
2464 uap = amba_ports[co->index]; in pl011_console_setup()
2466 return -ENODEV; in pl011_console_setup()
2469 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2471 ret = clk_prepare(uap->clk); in pl011_console_setup()
2475 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2478 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2479 if (plat->init) in pl011_console_setup()
2480 plat->init(); in pl011_console_setup()
2483 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2485 if (uap->vendor->fixed_options) { in pl011_console_setup()
2486 baud = uap->fixed_baud; in pl011_console_setup()
2495 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2499 * pl011_console_match - non-standard console matching
2514 * Returns 0 if console matches; otherwise non-zero to use default matching
2530 return -ENODEV; in pl011_console_match()
2533 return -ENODEV; in pl011_console_match()
2536 return -ENODEV; in pl011_console_match()
2545 port = &amba_ports[i]->port; in pl011_console_match()
2547 if (port->mapbase != addr) in pl011_console_match()
2550 co->index = i; in pl011_console_match()
2555 return -ENODEV; in pl011_console_match()
2566 .index = -1,
2574 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in qdf2400_e44_putc()
2576 writel(c, port->membase + UART01x_DR); in qdf2400_e44_putc()
2577 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) in qdf2400_e44_putc()
2583 struct earlycon_device *dev = con->data; in qdf2400_e44_early_write()
2585 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); in qdf2400_e44_early_write()
2590 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2592 if (port->iotype == UPIO_MEM32) in pl011_putc()
2593 writel(c, port->membase + UART01x_DR); in pl011_putc()
2595 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2596 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2602 struct earlycon_device *dev = con->data; in pl011_early_write()
2604 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2610 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) in pl011_getc()
2613 if (port->iotype == UPIO_MEM32) in pl011_getc()
2614 return readl(port->membase + UART01x_DR); in pl011_getc()
2616 return readb(port->membase + UART01x_DR); in pl011_getc()
2621 struct earlycon_device *dev = con->data; in pl011_early_read()
2625 ch = pl011_getc(&dev->port); in pl011_early_read()
2639 * On non-ACPI systems, earlycon is enabled by specifying
2653 if (!device->port.membase) in pl011_early_console_setup()
2654 return -ENODEV; in pl011_early_console_setup()
2656 device->con->write = pl011_early_write; in pl011_early_console_setup()
2657 device->con->read = pl011_early_read; in pl011_early_console_setup()
2664 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2673 * case, the SPCR code will detect the need for the E44 work-around,
2680 if (!device->port.membase) in qdf2400_e44_early_console_setup()
2681 return -ENODEV; in qdf2400_e44_early_console_setup()
2683 device->con->write = qdf2400_e44_early_write; in qdf2400_e44_early_console_setup()
2713 np = dev->of_node; in pl011_probe_dt_alias()
2730 …dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeratio… in pl011_probe_dt_alias()
2760 return -EBUSY; in pl011_find_free_port()
2775 uap->port.dev = dev; in pl011_setup_port()
2776 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2777 uap->port.membase = base; in pl011_setup_port()
2778 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2779 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); in pl011_setup_port()
2780 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2781 uap->port.line = index; in pl011_setup_port()
2783 ret = uart_get_rs485_mode(&uap->port); in pl011_setup_port()
2803 dev_err(uap->port.dev, in pl011_register_port()
2804 "Failed to register AMBA-PL011 driver\n"); in pl011_register_port()
2812 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2829 struct vendor_data *vendor = id->data; in pl011_probe()
2837 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), in pl011_probe()
2840 return -ENOMEM; in pl011_probe()
2842 uap->clk = devm_clk_get(&dev->dev, NULL); in pl011_probe()
2843 if (IS_ERR(uap->clk)) in pl011_probe()
2844 return PTR_ERR(uap->clk); in pl011_probe()
2846 uap->reg_offset = vendor->reg_offset; in pl011_probe()
2847 uap->vendor = vendor; in pl011_probe()
2848 uap->fifosize = vendor->get_fifosize(dev); in pl011_probe()
2849 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in pl011_probe()
2850 uap->port.irq = dev->irq[0]; in pl011_probe()
2851 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2852 uap->port.rs485_config = pl011_rs485_config; in pl011_probe()
2853 uap->port.rs485_supported = pl011_rs485_supported; in pl011_probe()
2854 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); in pl011_probe()
2856 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { in pl011_probe()
2859 uap->port.iotype = UPIO_MEM; in pl011_probe()
2862 uap->port.iotype = UPIO_MEM32; in pl011_probe()
2865 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", in pl011_probe()
2867 return -EINVAL; in pl011_probe()
2871 hrtimer_init(&uap->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in pl011_probe()
2872 hrtimer_init(&uap->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in pl011_probe()
2873 uap->trigger_start_tx.function = pl011_trigger_start_tx; in pl011_probe()
2874 uap->trigger_stop_tx.function = pl011_trigger_stop_tx; in pl011_probe()
2876 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); in pl011_probe()
2889 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2899 return -EINVAL; in pl011_suspend()
2901 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2909 return -EINVAL; in pl011_resume()
2911 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2925 uap->vendor = &vendor_qdt_qdf2400_e44; in qpdf2400_erratum44_workaround()
2944 if (pdev->dev.of_node) { in sbsa_uart_probe()
2945 struct device_node *np = pdev->dev.of_node; in sbsa_uart_probe()
2947 ret = of_property_read_u32(np, "current-speed", &baudrate); in sbsa_uart_probe()
2958 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), in sbsa_uart_probe()
2961 return -ENOMEM; in sbsa_uart_probe()
2966 uap->port.irq = ret; in sbsa_uart_probe()
2968 uap->vendor = &vendor_sbsa; in sbsa_uart_probe()
2969 qpdf2400_erratum44_workaround(&pdev->dev, uap); in sbsa_uart_probe()
2971 uap->reg_offset = uap->vendor->reg_offset; in sbsa_uart_probe()
2972 uap->fifosize = 32; in sbsa_uart_probe()
2973 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in sbsa_uart_probe()
2974 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2975 uap->fixed_baud = baudrate; in sbsa_uart_probe()
2977 snprintf(uap->type, sizeof(uap->type), "SBSA"); in sbsa_uart_probe()
2981 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); in sbsa_uart_probe()
2994 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()
2999 { .compatible = "arm,sbsa-uart", },
3015 .name = "sbsa-uart",
3041 .name = "uart-pl011",