Lines Matching +full:irq +full:- +full:syscfg
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/irq.h>
29 #include <linux/pinctrl/pinconf-generic.h>
36 #include "../pinctrl-utils.h"
37 #include "pinctrl-stm32.h"
150 return function - 1; in stm32_gpio_get_alt()
161 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
162 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
168 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
171 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
177 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
178 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
184 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
185 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
191 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
192 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
205 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
211 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
213 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
215 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
217 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
218 return -EINVAL; in stm32_gpio_request()
228 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
254 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
275 ret = -EINVAL; in stm32_gpio_get_direction()
285 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask()
292 if (bank->secure_control) { in stm32_gpio_init_valid_mask()
294 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); in stm32_gpio_init_valid_mask()
299 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
322 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger()
325 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */ in stm32_gpio_irq_trigger()
326 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
330 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
331 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
332 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
344 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type()
360 return -EINVAL; in stm32_gpio_set_type()
363 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
370 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources()
371 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
374 ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
378 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
380 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
381 irq_data->hwirq); in stm32_gpio_irq_request_resources()
390 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources()
392 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
418 if ((fwspec->param_count != 2) || in stm32_gpio_domain_translate()
419 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) in stm32_gpio_domain_translate()
420 return -EINVAL; in stm32_gpio_domain_translate()
422 *hwirq = fwspec->param[0]; in stm32_gpio_domain_translate()
423 *type = fwspec->param[1]; in stm32_gpio_domain_translate()
430 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate()
431 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
434 if (pctl->hwlock) { in stm32_gpio_domain_activate()
435 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_gpio_domain_activate()
438 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_gpio_domain_activate()
443 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
445 if (pctl->hwlock) in stm32_gpio_domain_activate()
446 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
455 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc()
458 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc()
459 irq_hw_number_t hwirq = fwspec->param[0]; in stm32_gpio_domain_alloc()
464 * Check first that the IRQ MUX of that line is free. in stm32_gpio_domain_alloc()
465 * gpio irq mux is shared between several banks, protect with a lock in stm32_gpio_domain_alloc()
467 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
469 if (pctl->irqmux_map & BIT(hwirq)) { in stm32_gpio_domain_alloc()
470 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); in stm32_gpio_domain_alloc()
471 ret = -EBUSY; in stm32_gpio_domain_alloc()
473 pctl->irqmux_map |= BIT(hwirq); in stm32_gpio_domain_alloc()
476 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_alloc()
480 parent_fwspec.fwnode = d->parent->fwnode; in stm32_gpio_domain_alloc()
482 parent_fwspec.param[0] = fwspec->param[0]; in stm32_gpio_domain_alloc()
483 parent_fwspec.param[1] = fwspec->param[1]; in stm32_gpio_domain_alloc()
494 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_free()
495 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free()
497 unsigned long flags, hwirq = irq_data->hwirq; in stm32_gpio_domain_free()
501 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
502 pctl->irqmux_map &= ~BIT(hwirq); in stm32_gpio_domain_free()
503 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_free()
519 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
520 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
522 if (grp->pin == pin) in stm32_pctrl_find_group_by_pin()
534 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_is_function_valid()
535 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_is_function_valid()
536 const struct stm32_desc_function *func = pin->functions; in stm32_pctrl_is_function_valid()
538 if (pin->pin.number != pin_num) in stm32_pctrl_is_function_valid()
542 if (func->num == fnum) in stm32_pctrl_is_function_valid()
550 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num); in stm32_pctrl_is_function_valid()
561 return -ENOSPC; in stm32_pctrl_dt_node_to_map_func()
564 (*map)[*num_maps].data.mux.group = grp->name; in stm32_pctrl_dt_node_to_map_func()
567 return -EINVAL; in stm32_pctrl_dt_node_to_map_func()
595 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", in stm32_pctrl_dt_subnode_to_map()
597 return -EINVAL; in stm32_pctrl_dt_subnode_to_map()
608 num_pins = pins->length / sizeof(u32); in stm32_pctrl_dt_subnode_to_map()
617 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
638 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
644 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
646 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
657 reserved_maps, num_maps, grp->name, in stm32_pctrl_dt_subnode_to_map()
697 return pctl->ngroups; in stm32_pctrl_get_groups_count()
705 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
715 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
750 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
751 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
759 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode()
766 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
768 if (pctl->hwlock) { in stm32_pmx_set_mode()
769 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pmx_set_mode()
772 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pmx_set_mode()
777 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
780 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
782 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
785 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
787 if (pctl->hwlock) in stm32_pmx_set_mode()
788 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pmx_set_mode()
793 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
806 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
808 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
812 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
816 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
825 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
831 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
833 return -EINVAL; in stm32_pmx_set_mux()
835 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); in stm32_pmx_set_mux()
837 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
838 return -EINVAL; in stm32_pmx_set_mux()
841 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
842 pin = stm32_gpio_pin(g->pin); in stm32_pmx_set_mux()
854 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction()
867 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_request()
868 return -EINVAL; in stm32_pmx_request()
871 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) { in stm32_pmx_request()
872 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio); in stm32_pmx_request()
873 return -EACCES; in stm32_pmx_request()
894 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving()
899 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
901 if (pctl->hwlock) { in stm32_pconf_set_driving()
902 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_driving()
905 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_driving()
910 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
913 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
915 if (pctl->hwlock) in stm32_pconf_set_driving()
916 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_driving()
921 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
932 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
934 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
937 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
945 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed()
950 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
952 if (pctl->hwlock) { in stm32_pconf_set_speed()
953 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_speed()
956 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_speed()
961 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
964 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
966 if (pctl->hwlock) in stm32_pconf_set_speed()
967 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_speed()
972 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
983 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
985 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
988 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
996 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias()
1001 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1003 if (pctl->hwlock) { in stm32_pconf_set_bias()
1004 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_bias()
1007 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_bias()
1012 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1015 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1017 if (pctl->hwlock) in stm32_pconf_set_bias()
1018 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_bias()
1023 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1034 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1036 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1039 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1050 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1053 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1056 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1059 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1075 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
1076 return -EINVAL; in stm32_pconf_parse_conf()
1079 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1082 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_parse_conf()
1083 dev_warn(pctl->dev, "Can't access gpio %d\n", pin); in stm32_pconf_parse_conf()
1084 return -EACCES; in stm32_pconf_parse_conf()
1111 ret = -ENOTSUPP; in stm32_pconf_parse_conf()
1123 *config = pctl->groups[group].config; in stm32_pconf_group_get()
1132 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
1136 mutex_lock(&pctldev->mutex); in stm32_pconf_group_set()
1137 ret = stm32_pconf_parse_conf(pctldev, g->pin, in stm32_pconf_group_set()
1140 mutex_unlock(&pctldev->mutex); in stm32_pconf_group_set()
1144 g->config = configs[i]; in stm32_pconf_group_set()
1170 struct stm32_desc_pin *pins = pctl->pins; in stm32_pconf_get_pin_desc_by_pin_number()
1173 for (i = 0; i < pctl->npins; i++) { in stm32_pconf_get_pin_desc_by_pin_number()
1174 if (pins->pin.number == pin_number) in stm32_pconf_get_pin_desc_by_pin_number()
1203 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1206 if (!gpiochip_line_is_valid(range->gc, offset)) { in stm32_pconf_dbg_show()
1220 seq_printf(s, "- %s - %s", in stm32_pconf_dbg_show()
1230 seq_printf(s, "- %s - %s - %s - %s %s", in stm32_pconf_dbg_show()
1245 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt, in stm32_pconf_dbg_show()
1246 pin_desc->functions[alt + 1].name, in stm32_pconf_dbg_show()
1269 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; in stm32_pctrl_get_desc_pin_from_gpio()
1274 if (stm32_pin_nb < pctl->npins) { in stm32_pctrl_get_desc_pin_from_gpio()
1275 pin_desc = pctl->pins + stm32_pin_nb; in stm32_pctrl_get_desc_pin_from_gpio()
1276 if (pin_desc->pin.number == stm32_pin_nb) in stm32_pctrl_get_desc_pin_from_gpio()
1281 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_get_desc_pin_from_gpio()
1282 pin_desc = pctl->pins + i; in stm32_pctrl_get_desc_pin_from_gpio()
1283 if (pin_desc->pin.number == stm32_pin_nb) in stm32_pctrl_get_desc_pin_from_gpio()
1291 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank()
1293 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1295 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
1302 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1303 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1306 return -ENODEV; in stm32_gpiolib_register_bank()
1308 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1309 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1310 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1312 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1314 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1316 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) { in stm32_gpiolib_register_bank()
1318 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1322 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args)) in stm32_gpiolib_register_bank()
1325 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1326 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1327 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1328 range->id = bank_nr; in stm32_gpiolib_register_bank()
1329 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1330 range->base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1331 range->npins = npins; in stm32_gpiolib_register_bank()
1332 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1333 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1334 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1337 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1340 bank->gpio_chip.base = -1; in stm32_gpiolib_register_bank()
1342 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1343 bank->gpio_chip.fwnode = fwnode; in stm32_gpiolib_register_bank()
1344 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1345 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1346 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1347 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1348 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1350 if (pctl->domain) { in stm32_gpiolib_register_bank()
1351 /* create irq hierarchical domain */ in stm32_gpiolib_register_bank()
1352 bank->fwnode = fwnode; in stm32_gpiolib_register_bank()
1354 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1355 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1358 if (!bank->domain) in stm32_gpiolib_register_bank()
1359 return -ENODEV; in stm32_gpiolib_register_bank()
1364 return -ENOMEM; in stm32_gpiolib_register_bank()
1368 if (stm32_pin && stm32_pin->pin.name) { in stm32_gpiolib_register_bank()
1369 names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name); in stm32_gpiolib_register_bank()
1371 return -ENOMEM; in stm32_gpiolib_register_bank()
1377 bank->gpio_chip.names = (const char * const *)names; in stm32_gpiolib_register_bank()
1379 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1385 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1391 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_get_irq_domain()
1395 if (!of_property_present(np, "interrupt-parent")) in stm32_pctrl_get_irq_domain()
1400 return ERR_PTR(-ENXIO); in stm32_pctrl_get_irq_domain()
1406 return ERR_PTR(-EPROBE_DEFER); in stm32_pctrl_get_irq_domain()
1414 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_dt_setup_irq()
1415 struct device *dev = &pdev->dev; in stm32_pctrl_dt_setup_irq()
1420 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1421 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1422 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1424 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1426 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); in stm32_pctrl_dt_setup_irq()
1430 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); in stm32_pctrl_dt_setup_irq()
1441 mux.msb = mux.lsb + mask_width - 1; in stm32_pctrl_dt_setup_irq()
1446 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1447 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1448 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1459 pctl->ngroups = pctl->npins; in stm32_pctrl_build_state()
1462 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1463 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1464 if (!pctl->groups) in stm32_pctrl_build_state()
1465 return -ENOMEM; in stm32_pctrl_build_state()
1468 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1469 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1470 if (!pctl->grp_names) in stm32_pctrl_build_state()
1471 return -ENOMEM; in stm32_pctrl_build_state()
1473 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_build_state()
1474 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_build_state()
1475 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1477 group->name = pin->pin.name; in stm32_pctrl_build_state()
1478 group->pin = pin->pin.number; in stm32_pctrl_build_state()
1479 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1491 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_create_pins_tab()
1492 p = pctl->match_data->pins + i; in stm32_pctrl_create_pins_tab()
1493 if (pctl->pkg && !(pctl->pkg & p->pkg)) in stm32_pctrl_create_pins_tab()
1495 pins->pin = p->pin; in stm32_pctrl_create_pins_tab()
1496 memcpy((struct stm32_desc_pin *)pins->functions, p->functions, in stm32_pctrl_create_pins_tab()
1502 pctl->npins = nb_pins_available; in stm32_pctrl_create_pins_tab()
1511 struct device *dev = &pdev->dev; in stm32_pctl_probe()
1519 return -EINVAL; in stm32_pctl_probe()
1523 return -ENOMEM; in stm32_pctl_probe()
1527 /* check for IRQ controller (may require deferred probe) */ in stm32_pctl_probe()
1528 pctl->domain = stm32_pctrl_get_irq_domain(pdev); in stm32_pctl_probe()
1529 if (IS_ERR(pctl->domain)) in stm32_pctl_probe()
1530 return PTR_ERR(pctl->domain); in stm32_pctl_probe()
1531 if (!pctl->domain) in stm32_pctl_probe()
1535 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); in stm32_pctl_probe()
1537 if (hwlock_id == -EPROBE_DEFER) in stm32_pctl_probe()
1540 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); in stm32_pctl_probe()
1543 spin_lock_init(&pctl->irqmux_lock); in stm32_pctl_probe()
1545 pctl->dev = dev; in stm32_pctl_probe()
1546 pctl->match_data = match_data; in stm32_pctl_probe()
1549 if (!device_property_read_u32(dev, "st,package", &pctl->pkg)) in stm32_pctl_probe()
1550 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); in stm32_pctl_probe()
1552 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, in stm32_pctl_probe()
1553 sizeof(*pctl->pins), GFP_KERNEL); in stm32_pctl_probe()
1554 if (!pctl->pins) in stm32_pctl_probe()
1555 return -ENOMEM; in stm32_pctl_probe()
1557 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); in stm32_pctl_probe()
1564 return -EINVAL; in stm32_pctl_probe()
1567 if (pctl->domain) { in stm32_pctl_probe()
1573 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), in stm32_pctl_probe()
1576 return -ENOMEM; in stm32_pctl_probe()
1578 for (i = 0; i < pctl->npins; i++) in stm32_pctl_probe()
1579 pins[i] = pctl->pins[i].pin; in stm32_pctl_probe()
1581 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1582 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1583 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1584 pctl->pctl_desc.npins = pctl->npins; in stm32_pctl_probe()
1585 pctl->pctl_desc.link_consumers = true; in stm32_pctl_probe()
1586 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1587 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1588 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1589 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1591 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1594 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1595 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in stm32_pctl_probe()
1596 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1602 return -EINVAL; in stm32_pctl_probe()
1604 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1606 if (!pctl->banks) in stm32_pctl_probe()
1607 return -ENOMEM; in stm32_pctl_probe()
1609 pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks), in stm32_pctl_probe()
1611 if (!pctl->clks) in stm32_pctl_probe()
1612 return -ENOMEM; in stm32_pctl_probe()
1616 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1619 bank->rstc = of_reset_control_get_exclusive(np, NULL); in stm32_pctl_probe()
1620 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { in stm32_pctl_probe()
1622 return -EPROBE_DEFER; in stm32_pctl_probe()
1625 pctl->clks[i].clk = of_clk_get_by_name(np, NULL); in stm32_pctl_probe()
1626 if (IS_ERR(pctl->clks[i].clk)) { in stm32_pctl_probe()
1628 return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk), in stm32_pctl_probe()
1631 pctl->clks[i].id = "pctl"; in stm32_pctl_probe()
1635 ret = clk_bulk_prepare_enable(banks, pctl->clks); in stm32_pctl_probe()
1648 pctl->nbanks++; in stm32_pctl_probe()
1655 for (i = 0; i < pctl->nbanks; i++) { in stm32_pctl_probe()
1656 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1658 gpiochip_remove(&bank->gpio_chip); in stm32_pctl_probe()
1661 clk_bulk_disable_unprepare(banks, pctl->clks); in stm32_pctl_probe()
1668 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1675 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1679 if (!gpiochip_line_is_valid(range->gc, offset)) in stm32_pinctrl_restore_gpio_regs()
1682 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); in stm32_pinctrl_restore_gpio_regs()
1684 if (!desc || (!pin_is_irq && !desc->gpio_owner)) in stm32_pinctrl_restore_gpio_regs()
1687 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1689 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1691 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1699 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1704 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1710 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1716 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1723 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()
1732 clk_bulk_disable(pctl->nbanks, pctl->clks); in stm32_pinctrl_suspend()
1740 struct stm32_pinctrl_group *g = pctl->groups; in stm32_pinctrl_resume()
1743 ret = clk_bulk_enable(pctl->nbanks, pctl->clks); in stm32_pinctrl_resume()
1747 for (i = 0; i < pctl->ngroups; i++, g++) in stm32_pinctrl_resume()
1748 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); in stm32_pinctrl_resume()