Lines Matching +full:pin +full:- +full:ctrl +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
61 if (bank->eint_mask_offset) in exynos_irq_mask()
62 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
64 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
66 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
67 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
68 "unable to enable clock for masking IRQ\n"); in exynos_irq_mask()
72 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
74 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
75 mask |= 1 << irqd->hwirq; in exynos_irq_mask()
76 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
78 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
80 clk_disable(bank->drvdata->pclk); in exynos_irq_mask()
90 if (bank->eint_pend_offset) in exynos_irq_ack()
91 reg_pend = bank->pctl_offset + bank->eint_pend_offset; in exynos_irq_ack()
93 reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
95 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_ack()
96 dev_err(bank->gpio_chip.parent, in exynos_irq_ack()
97 "unable to enable clock to ack IRQ\n"); in exynos_irq_ack()
101 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
103 clk_disable(bank->drvdata->pclk); in exynos_irq_ack()
118 * If we don't do this we'll get a double-interrupt. Level triggered in exynos_irq_unmask()
126 if (bank->eint_mask_offset) in exynos_irq_unmask()
127 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_unmask()
129 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
131 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_unmask()
132 dev_err(bank->gpio_chip.parent, in exynos_irq_unmask()
133 "unable to enable clock for unmasking IRQ\n"); in exynos_irq_unmask()
137 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_unmask()
139 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
140 mask &= ~(1 << irqd->hwirq); in exynos_irq_unmask()
141 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
143 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_unmask()
145 clk_disable(bank->drvdata->pclk); in exynos_irq_unmask()
153 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; in exynos_irq_set_type()
176 return -EINVAL; in exynos_irq_set_type()
184 if (bank->eint_con_offset) in exynos_irq_set_type()
185 reg_con = bank->pctl_offset + bank->eint_con_offset; in exynos_irq_set_type()
187 reg_con = our_chip->eint_con + bank->eint_offset; in exynos_irq_set_type()
189 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_set_type()
191 dev_err(bank->gpio_chip.parent, in exynos_irq_set_type()
192 "unable to enable clock for configuring IRQ type\n"); in exynos_irq_set_type()
196 con = readl(bank->eint_base + reg_con); in exynos_irq_set_type()
199 writel(con, bank->eint_base + reg_con); in exynos_irq_set_type()
201 clk_disable(bank->drvdata->pclk); in exynos_irq_set_type()
210 struct samsung_pinctrl_drv_data *d = bank->drvdata; in exynos_irq_set_affinity()
211 struct irq_data *parent = irq_get_irq_data(d->irq); in exynos_irq_set_affinity()
214 return parent->chip->irq_set_affinity(parent, dest, force); in exynos_irq_set_affinity()
216 return -EINVAL; in exynos_irq_set_affinity()
222 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_request_resources()
227 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_request_resources()
229 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
230 "unable to lock pin %s-%lu IRQ\n", in exynos_irq_request_resources()
231 bank->name, irqd->hwirq); in exynos_irq_request_resources()
235 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
236 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
237 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; in exynos_irq_request_resources()
239 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_request_resources()
241 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
242 "unable to enable clock for configuring pin %s-%lu\n", in exynos_irq_request_resources()
243 bank->name, irqd->hwirq); in exynos_irq_request_resources()
247 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_request_resources()
249 con = readl(bank->pctl_base + reg_con); in exynos_irq_request_resources()
252 writel(con, bank->pctl_base + reg_con); in exynos_irq_request_resources()
254 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_request_resources()
256 clk_disable(bank->drvdata->pclk); in exynos_irq_request_resources()
264 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_release_resources()
268 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
269 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
270 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; in exynos_irq_release_resources()
272 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_release_resources()
273 dev_err(bank->gpio_chip.parent, in exynos_irq_release_resources()
274 "unable to enable clock for deconfiguring pin %s-%lu\n", in exynos_irq_release_resources()
275 bank->name, irqd->hwirq); in exynos_irq_release_resources()
279 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_release_resources()
281 con = readl(bank->pctl_base + reg_con); in exynos_irq_release_resources()
284 writel(con, bank->pctl_base + reg_con); in exynos_irq_release_resources()
286 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_release_resources()
288 clk_disable(bank->drvdata->pclk); in exynos_irq_release_resources()
290 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_release_resources()
316 struct samsung_pin_bank *b = h->host_data; in exynos_eint_irq_map()
319 irq_set_chip_and_handler(virq, &b->irq_chip->chip, in exynos_eint_irq_map()
335 struct samsung_pin_bank *bank = d->pin_banks; in exynos_eint_gpio_irq()
336 unsigned int svc, group, pin; in exynos_eint_gpio_irq() local
339 if (clk_enable(bank->drvdata->pclk)) { in exynos_eint_gpio_irq()
340 dev_err(bank->gpio_chip.parent, in exynos_eint_gpio_irq()
341 "unable to enable clock for handling IRQ\n"); in exynos_eint_gpio_irq()
345 if (bank->eint_con_offset) in exynos_eint_gpio_irq()
346 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); in exynos_eint_gpio_irq()
348 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); in exynos_eint_gpio_irq()
350 clk_disable(bank->drvdata->pclk); in exynos_eint_gpio_irq()
353 pin = svc & EXYNOS_SVC_NUM_MASK; in exynos_eint_gpio_irq()
357 bank += (group - 1); in exynos_eint_gpio_irq()
359 ret = generic_handle_domain_irq(bank->irq_domain, pin); in exynos_eint_gpio_irq()
374 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
380 struct device *dev = d->dev; in exynos_eint_gpio_init()
384 if (!d->irq) { in exynos_eint_gpio_init()
386 return -EINVAL; in exynos_eint_gpio_init()
389 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, in exynos_eint_gpio_init()
393 return -ENXIO; in exynos_eint_gpio_init()
396 bank = d->pin_banks; in exynos_eint_gpio_init()
397 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_gpio_init()
398 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
401 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, in exynos_eint_gpio_init()
402 sizeof(*bank->irq_chip), GFP_KERNEL); in exynos_eint_gpio_init()
403 if (!bank->irq_chip) { in exynos_eint_gpio_init()
404 ret = -ENOMEM; in exynos_eint_gpio_init()
407 bank->irq_chip->chip.name = bank->name; in exynos_eint_gpio_init()
409 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_gpio_init()
410 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_gpio_init()
411 if (!bank->irq_domain) { in exynos_eint_gpio_init()
413 ret = -ENXIO; in exynos_eint_gpio_init()
417 bank->soc_priv = devm_kzalloc(d->dev, in exynos_eint_gpio_init()
419 if (!bank->soc_priv) { in exynos_eint_gpio_init()
420 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
421 ret = -ENOMEM; in exynos_eint_gpio_init()
430 for (--i, --bank; i >= 0; --i, --bank) { in exynos_eint_gpio_init()
431 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
433 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
444 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
446 pr_info("wake %s for irq %u (%s-%lu)\n", str_enabled_disabled(on), in exynos_wkup_irq_set_wake()
447 irqd->irq, bank->name, irqd->hwirq); in exynos_wkup_irq_set_wake()
450 *our_chip->eint_wake_mask_value |= bit; in exynos_wkup_irq_set_wake()
452 *our_chip->eint_wake_mask_value &= ~bit; in exynos_wkup_irq_set_wake()
463 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { in exynos_pinctrl_set_eint_wakeup_mask()
464 dev_warn(drvdata->dev, in exynos_pinctrl_set_eint_wakeup_mask()
465 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in exynos_pinctrl_set_eint_wakeup_mask()
469 pmu_regs = drvdata->retention_ctrl->priv; in exynos_pinctrl_set_eint_wakeup_mask()
470 dev_info(drvdata->dev, in exynos_pinctrl_set_eint_wakeup_mask()
472 *irq_chip->eint_wake_mask_value); in exynos_pinctrl_set_eint_wakeup_mask()
474 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, in exynos_pinctrl_set_eint_wakeup_mask()
475 *irq_chip->eint_wake_mask_value); in exynos_pinctrl_set_eint_wakeup_mask()
485 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { in s5pv210_pinctrl_set_eint_wakeup_mask()
486 dev_warn(drvdata->dev, in s5pv210_pinctrl_set_eint_wakeup_mask()
487 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in s5pv210_pinctrl_set_eint_wakeup_mask()
492 clk_base = (void __iomem *) drvdata->retention_ctrl->priv; in s5pv210_pinctrl_set_eint_wakeup_mask()
494 __raw_writel(*irq_chip->eint_wake_mask_value, in s5pv210_pinctrl_set_eint_wakeup_mask()
495 clk_base + irq_chip->eint_wake_mask_reg); in s5pv210_pinctrl_set_eint_wakeup_mask()
578 { .compatible = "samsung,s5pv210-wakeup-eint",
580 { .compatible = "samsung,exynos4210-wakeup-eint",
582 { .compatible = "samsung,exynos7-wakeup-eint",
584 { .compatible = "samsung,exynos850-wakeup-eint",
586 { .compatible = "samsung,exynosautov9-wakeup-eint",
588 { .compatible = "samsung,exynosautov920-wakeup-eint",
597 struct samsung_pin_bank *bank = eintd->bank; in exynos_irq_eint0_15()
602 generic_handle_domain_irq(bank->irq_domain, eintd->irq); in exynos_irq_eint0_15()
613 irq = fls(pend) - 1; in exynos_irq_demux_eint()
631 * just enable the clock once here, to avoid an enable/disable dance for in exynos_irq_demux_eint16_31()
634 if (eintd->nr_banks) { in exynos_irq_demux_eint16_31()
635 struct samsung_pin_bank *b = eintd->banks[0]; in exynos_irq_demux_eint16_31()
637 if (clk_enable(b->drvdata->pclk)) { in exynos_irq_demux_eint16_31()
638 dev_err(b->gpio_chip.parent, in exynos_irq_demux_eint16_31()
639 "unable to enable clock for pending IRQs\n"); in exynos_irq_demux_eint16_31()
644 for (i = 0; i < eintd->nr_banks; ++i) { in exynos_irq_demux_eint16_31()
645 struct samsung_pin_bank *b = eintd->banks[i]; in exynos_irq_demux_eint16_31()
646 pend = readl(b->eint_base + b->irq_chip->eint_pend in exynos_irq_demux_eint16_31()
647 + b->eint_offset); in exynos_irq_demux_eint16_31()
648 mask = readl(b->eint_base + b->irq_chip->eint_mask in exynos_irq_demux_eint16_31()
649 + b->eint_offset); in exynos_irq_demux_eint16_31()
650 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); in exynos_irq_demux_eint16_31()
653 if (eintd->nr_banks) in exynos_irq_demux_eint16_31()
654 clk_disable(eintd->banks[0]->drvdata->pclk); in exynos_irq_demux_eint16_31()
661 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
666 struct device *dev = d->dev; in exynos_eint_wkup_init()
677 for_each_child_of_node(dev->of_node, np) { in exynos_eint_wkup_init()
682 irq_chip = match->data; in exynos_eint_wkup_init()
688 return -ENODEV; in exynos_eint_wkup_init()
690 bank = d->pin_banks; in exynos_eint_wkup_init()
691 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
692 if (bank->eint_type != EINT_TYPE_WKUP) in exynos_eint_wkup_init()
695 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), in exynos_eint_wkup_init()
697 if (!bank->irq_chip) in exynos_eint_wkup_init()
698 return -ENOMEM; in exynos_eint_wkup_init()
699 bank->irq_chip->chip.name = bank->name; in exynos_eint_wkup_init()
701 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_wkup_init()
702 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_wkup_init()
703 if (!bank->irq_domain) { in exynos_eint_wkup_init()
705 return -ENXIO; in exynos_eint_wkup_init()
708 if (!fwnode_property_present(bank->fwnode, "interrupts")) { in exynos_eint_wkup_init()
709 bank->eint_type = EINT_TYPE_WKUP_MUX; in exynos_eint_wkup_init()
715 bank->nr_pins, sizeof(*weint_data), in exynos_eint_wkup_init()
718 return -ENOMEM; in exynos_eint_wkup_init()
720 for (idx = 0; idx < bank->nr_pins; ++idx) { in exynos_eint_wkup_init()
721 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); in exynos_eint_wkup_init()
723 dev_err(dev, "irq number for eint-%s-%d not found\n", in exynos_eint_wkup_init()
724 bank->name, idx); in exynos_eint_wkup_init()
747 return -ENOMEM; in exynos_eint_wkup_init()
748 muxed_data->nr_banks = muxed_banks; in exynos_eint_wkup_init()
753 bank = d->pin_banks; in exynos_eint_wkup_init()
755 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
756 if (bank->eint_type != EINT_TYPE_WKUP_MUX) in exynos_eint_wkup_init()
759 muxed_data->banks[idx++] = bank; in exynos_eint_wkup_init()
769 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend_bank()
770 const void __iomem *regs = bank->eint_base; in exynos_pinctrl_suspend_bank()
772 if (clk_enable(bank->drvdata->pclk)) { in exynos_pinctrl_suspend_bank()
773 dev_err(bank->gpio_chip.parent, in exynos_pinctrl_suspend_bank()
774 "unable to enable clock for saving state\n"); in exynos_pinctrl_suspend_bank()
778 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET in exynos_pinctrl_suspend_bank()
779 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
780 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend_bank()
781 + 2 * bank->eint_offset); in exynos_pinctrl_suspend_bank()
782 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend_bank()
783 + 2 * bank->eint_offset + 4); in exynos_pinctrl_suspend_bank()
784 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend_bank()
785 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
787 clk_disable(bank->drvdata->pclk); in exynos_pinctrl_suspend_bank()
789 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynos_pinctrl_suspend_bank()
790 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend_bank()
791 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend_bank()
792 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynos_pinctrl_suspend_bank()
798 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosauto_pinctrl_suspend_bank()
799 const void __iomem *regs = bank->eint_base; in exynosauto_pinctrl_suspend_bank()
801 if (clk_enable(bank->drvdata->pclk)) { in exynosauto_pinctrl_suspend_bank()
802 dev_err(bank->gpio_chip.parent, in exynosauto_pinctrl_suspend_bank()
803 "unable to enable clock for saving state\n"); in exynosauto_pinctrl_suspend_bank()
807 save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); in exynosauto_pinctrl_suspend_bank()
808 save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); in exynosauto_pinctrl_suspend_bank()
810 clk_disable(bank->drvdata->pclk); in exynosauto_pinctrl_suspend_bank()
812 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynosauto_pinctrl_suspend_bank()
813 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynosauto_pinctrl_suspend_bank()
818 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_suspend()
822 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { in exynos_pinctrl_suspend()
823 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_suspend()
824 if (bank->eint_con_offset) in exynos_pinctrl_suspend()
829 else if (bank->eint_type == EINT_TYPE_WKUP) { in exynos_pinctrl_suspend()
831 irq_chip = bank->irq_chip; in exynos_pinctrl_suspend()
832 irq_chip->set_eint_wakeup_mask(drvdata, in exynos_pinctrl_suspend()
843 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume_bank()
844 void __iomem *regs = bank->eint_base; in exynos_pinctrl_resume_bank()
846 if (clk_enable(bank->drvdata->pclk)) { in exynos_pinctrl_resume_bank()
847 dev_err(bank->gpio_chip.parent, in exynos_pinctrl_resume_bank()
848 "unable to enable clock for restoring state\n"); in exynos_pinctrl_resume_bank()
852 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
854 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume_bank()
855 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
857 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume_bank()
858 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
860 + 2 * bank->eint_offset + 4), save->eint_fltcon1); in exynos_pinctrl_resume_bank()
861 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
862 readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
863 + bank->eint_offset), save->eint_mask); in exynos_pinctrl_resume_bank()
865 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET in exynos_pinctrl_resume_bank()
866 + bank->eint_offset); in exynos_pinctrl_resume_bank()
867 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_resume_bank()
868 + 2 * bank->eint_offset); in exynos_pinctrl_resume_bank()
869 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_resume_bank()
870 + 2 * bank->eint_offset + 4); in exynos_pinctrl_resume_bank()
871 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
872 + bank->eint_offset); in exynos_pinctrl_resume_bank()
874 clk_disable(bank->drvdata->pclk); in exynos_pinctrl_resume_bank()
880 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosauto_pinctrl_resume_bank()
881 void __iomem *regs = bank->eint_base; in exynosauto_pinctrl_resume_bank()
883 if (clk_enable(bank->drvdata->pclk)) { in exynosauto_pinctrl_resume_bank()
884 dev_err(bank->gpio_chip.parent, in exynosauto_pinctrl_resume_bank()
885 "unable to enable clock for restoring state\n"); in exynosauto_pinctrl_resume_bank()
889 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynosauto_pinctrl_resume_bank()
890 readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); in exynosauto_pinctrl_resume_bank()
891 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynosauto_pinctrl_resume_bank()
892 readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask); in exynosauto_pinctrl_resume_bank()
894 writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); in exynosauto_pinctrl_resume_bank()
895 writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); in exynosauto_pinctrl_resume_bank()
897 clk_disable(bank->drvdata->pclk); in exynosauto_pinctrl_resume_bank()
902 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_resume()
905 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) in exynos_pinctrl_resume()
906 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_resume()
907 if (bank->eint_con_offset) in exynos_pinctrl_resume()
916 if (drvdata->retention_ctrl->refcnt) in exynos_retention_enable()
917 atomic_inc(drvdata->retention_ctrl->refcnt); in exynos_retention_enable()
922 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; in exynos_retention_disable() local
923 struct regmap *pmu_regs = ctrl->priv; in exynos_retention_disable()
926 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) in exynos_retention_disable()
929 for (i = 0; i < ctrl->nr_regs; i++) in exynos_retention_disable()
930 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); in exynos_retention_disable()
937 struct samsung_retention_ctrl *ctrl; in exynos_retention_init() local
941 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in exynos_retention_init()
942 if (!ctrl) in exynos_retention_init()
943 return ERR_PTR(-ENOMEM); in exynos_retention_init()
949 ctrl->priv = pmu_regs; in exynos_retention_init()
950 ctrl->regs = data->regs; in exynos_retention_init()
951 ctrl->nr_regs = data->nr_regs; in exynos_retention_init()
952 ctrl->value = data->value; in exynos_retention_init()
953 ctrl->refcnt = data->refcnt; in exynos_retention_init()
954 ctrl->enable = exynos_retention_enable; in exynos_retention_init()
955 ctrl->disable = exynos_retention_disable; in exynos_retention_init()
958 for (i = 0; i < ctrl->nr_regs; i++) in exynos_retention_init()
959 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); in exynos_retention_init()
961 return ctrl; in exynos_retention_init()