Lines Matching full:pctrl
296 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
297 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
298 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
299 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
368 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_get_variable_pin_cfg() argument
375 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { in rzg2l_pinctrl_get_variable_pin_cfg()
376 u64 cfg = pctrl->data->variable_pin_cfg[i]; in rzg2l_pinctrl_get_variable_pin_cfg()
478 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) in rzg2l_pmc_writeb() argument
480 writeb(val, pctrl->base + offset); in rzg2l_pmc_writeb()
483 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) in rzv2h_pmc_writeb() argument
485 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pmc_writeb()
488 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
489 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
490 writeb(val, pctrl->base + offset); in rzv2h_pmc_writeb()
491 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pmc_writeb()
494 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_set_pfc_mode() argument
500 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
503 reg = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
505 writew(reg, pctrl->base + PM(off)); in rzg2l_pinctrl_set_pfc_mode()
507 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_set_pfc_mode()
510 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
511 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
514 reg = readl(pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
516 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); in rzg2l_pinctrl_set_pfc_mode()
519 reg = readb(pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
520 writeb(reg | BIT(pin), pctrl->base + PMC(off)); in rzg2l_pinctrl_set_pfc_mode()
522 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_set_pfc_mode()
524 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
531 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_set_mux() local
532 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_set_mux()
549 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; in rzg2l_pinctrl_set_mux()
553 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", in rzg2l_pinctrl_set_mux()
556 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); in rzg2l_pinctrl_set_mux()
589 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_subnode_to_map() local
613 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
623 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
633 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
669 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
670 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
672 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
690 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", in rzg2l_dt_subnode_to_map()
710 mutex_lock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
730 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
737 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
744 mutex_unlock(&pctrl->mutex); in rzg2l_dt_subnode_to_map()
773 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_node_to_map() local
798 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
807 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, in rzg2l_validate_gpio_pin() argument
814 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) in rzg2l_validate_gpio_pin()
817 data = pctrl->data->port_pin_configs[port]; in rzg2l_validate_gpio_pin()
824 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_read_pin_config() argument
827 void __iomem *addr = pctrl->base + offset; in rzg2l_read_pin_config()
838 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_rmw_pin_config() argument
841 void __iomem *addr = pctrl->base + offset; in rzg2l_rmw_pin_config()
851 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
854 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_rmw_pin_config()
873 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) in rzg2l_get_power_source() argument
875 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_get_power_source()
881 return pctrl->settings[pin].power_source; in rzg2l_get_power_source()
887 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
901 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) in rzg2l_set_power_source() argument
903 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_set_power_source()
909 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
933 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
934 pctrl->settings[pin].power_source = ps; in rzg2l_set_power_source()
1008 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, in rzg2l_ds_is_supported() argument
1012 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_ds_is_supported()
1040 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg2l_pin_to_oen_bit() argument
1042 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg2l_pin_to_oen_bit()
1046 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg2l_pin_to_oen_bit()
1061 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg2l_read_oen() argument
1065 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); in rzg2l_read_oen()
1069 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg2l_read_oen()
1072 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzg2l_write_oen() argument
1078 bit = rzg2l_pin_to_oen_bit(pctrl, _pin); in rzg2l_write_oen()
1082 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_write_oen()
1083 val = readb(pctrl->base + ETH_MODE); in rzg2l_write_oen()
1088 writeb(val, pctrl->base + ETH_MODE); in rzg2l_write_oen()
1089 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_write_oen()
1094 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg3s_pin_to_oen_bit() argument
1096 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; in rzg3s_pin_to_oen_bit()
1104 if (pin > pctrl->data->hwcfg->oen_max_pin) in rzg3s_pin_to_oen_bit()
1108 if (port == pctrl->data->hwcfg->oen_max_port) in rzg3s_pin_to_oen_bit()
1114 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzg3s_oen_read() argument
1118 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); in rzg3s_oen_read()
1122 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); in rzg3s_oen_read()
1125 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzg3s_oen_write() argument
1131 bit = rzg3s_pin_to_oen_bit(pctrl, _pin); in rzg3s_oen_write()
1135 spin_lock_irqsave(&pctrl->lock, flags); in rzg3s_oen_write()
1136 val = readb(pctrl->base + ETH_MODE); in rzg3s_oen_write()
1141 writeb(val, pctrl->base + ETH_MODE); in rzg3s_oen_write()
1142 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg3s_oen_write()
1212 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzv2h_pin_to_oen_bit() argument
1217 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; in rzv2h_pin_to_oen_bit()
1229 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) in rzv2h_oen_read() argument
1233 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); in rzv2h_oen_read()
1235 return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); in rzv2h_oen_read()
1238 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) in rzv2h_oen_write() argument
1240 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzv2h_oen_write()
1246 bit = rzv2h_pin_to_oen_bit(pctrl, _pin); in rzv2h_oen_write()
1247 spin_lock_irqsave(&pctrl->lock, flags); in rzv2h_oen_write()
1248 val = readb(pctrl->base + PFC_OEN); in rzv2h_oen_write()
1254 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_oen_write()
1255 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1256 writeb(val, pctrl->base + PFC_OEN); in rzv2h_oen_write()
1257 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); in rzv2h_oen_write()
1258 spin_unlock_irqrestore(&pctrl->lock, flags); in rzv2h_oen_write()
1267 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_get() local
1268 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_get()
1269 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
1288 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_get()
1296 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); in rzg2l_pinctrl_pinconf_get()
1304 if (!pctrl->data->oen_read) in rzg2l_pinctrl_pinconf_get()
1306 arg = pctrl->data->oen_read(pctrl, _pin); in rzg2l_pinctrl_pinconf_get()
1312 ret = rzg2l_get_power_source(pctrl, _pin, cfg); in rzg2l_pinctrl_pinconf_get()
1322 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); in rzg2l_pinctrl_pinconf_get()
1331 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); in rzg2l_pinctrl_pinconf_get()
1332 ret = pctrl->data->hw_to_bias_param(arg); in rzg2l_pinctrl_pinconf_get()
1348 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1365 ret = rzg2l_get_power_source(pctrl, _pin, cfg); in rzg2l_pinctrl_pinconf_get()
1369 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1380 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1390 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); in rzg2l_pinctrl_pinconf_get()
1401 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); in rzg2l_pinctrl_pinconf_get()
1410 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); in rzg2l_pinctrl_pinconf_get()
1427 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_set() local
1428 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
1429 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_pinconf_set()
1430 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; in rzg2l_pinctrl_pinconf_set()
1448 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) in rzg2l_pinctrl_pinconf_set()
1461 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); in rzg2l_pinctrl_pinconf_set()
1467 if (!pctrl->data->oen_write) in rzg2l_pinctrl_pinconf_set()
1469 ret = pctrl->data->oen_write(pctrl, _pin, !!arg); in rzg2l_pinctrl_pinconf_set()
1482 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1491 ret = pctrl->data->bias_param_to_hw(param); in rzg2l_pinctrl_pinconf_set()
1495 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); in rzg2l_pinctrl_pinconf_set()
1510 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
1532 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); in rzg2l_pinctrl_pinconf_set()
1540 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, in rzg2l_pinctrl_pinconf_set()
1548 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1557 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); in rzg2l_pinctrl_pinconf_set()
1566 if (settings.power_source != pctrl->settings[_pin].power_source) { in rzg2l_pinctrl_pinconf_set()
1572 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); in rzg2l_pinctrl_pinconf_set()
1578 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { in rzg2l_pinctrl_pinconf_set()
1583 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, in rzg2l_pinctrl_pinconf_set()
1594 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); in rzg2l_pinctrl_pinconf_set()
1595 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; in rzg2l_pinctrl_pinconf_set()
1678 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_request() local
1679 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_request()
1688 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); in rzg2l_gpio_request()
1696 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
1699 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_request()
1701 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); in rzg2l_gpio_request()
1703 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
1708 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, in rzg2l_gpio_set_direction() argument
1711 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set_direction()
1718 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1720 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1724 writew(reg16, pctrl->base + PM(off)); in rzg2l_gpio_set_direction()
1726 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
1731 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get_direction() local
1732 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get_direction()
1737 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { in rzg2l_gpio_get_direction()
1740 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get_direction()
1752 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_input() local
1754 rzg2l_gpio_set_direction(pctrl, offset, false); in rzg2l_gpio_direction_input()
1762 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_set() local
1763 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_set()
1770 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
1772 reg8 = readb(pctrl->base + P(off)); in rzg2l_gpio_set()
1775 writeb(reg8 | BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1777 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); in rzg2l_gpio_set()
1779 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
1785 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_output() local
1788 rzg2l_gpio_set_direction(pctrl, offset, true); in rzg2l_gpio_direction_output()
1795 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get() local
1796 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_get()
1802 reg16 = readw(pctrl->base + PM(off)); in rzg2l_gpio_get()
1806 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); in rzg2l_gpio_get()
1808 return !!(readb(pctrl->base + P(off)) & BIT(bit)); in rzg2l_gpio_get()
2399 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_get_gpioint() argument
2401 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; in rzg2l_gpio_get_gpioint()
2402 const struct rzg2l_pinctrl_data *data = pctrl->data; in rzg2l_gpio_get_gpioint()
2425 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, in rzg2l_gpio_irq_endisable() argument
2428 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; in rzg2l_gpio_irq_endisable()
2435 addr = pctrl->base + ISEL(off); in rzg2l_gpio_irq_endisable()
2441 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2446 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_endisable()
2487 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_set_wake() local
2499 atomic_inc(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2501 atomic_dec(&pctrl->wakeup_path); in rzg2l_gpio_irq_set_wake()
2523 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_interrupt_input_mode() local
2524 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; in rzg2l_gpio_interrupt_input_mode()
2531 reg8 = readb(pctrl->base + PMC(off)); in rzg2l_gpio_interrupt_input_mode()
2547 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_gpio_child_to_parent_hwirq() local
2552 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); in rzg2l_gpio_child_to_parent_hwirq()
2560 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2561 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); in rzg2l_gpio_child_to_parent_hwirq()
2562 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_child_to_parent_hwirq()
2568 rzg2l_gpio_irq_endisable(pctrl, child, true); in rzg2l_gpio_child_to_parent_hwirq()
2569 pctrl->hwirq[irq] = child; in rzg2l_gpio_child_to_parent_hwirq()
2570 irq += pctrl->data->hwcfg->tint_start_index; in rzg2l_gpio_child_to_parent_hwirq()
2582 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_irq_restore() argument
2584 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; in rzg2l_gpio_irq_restore()
2592 if (!pctrl->hwirq[i]) in rzg2l_gpio_irq_restore()
2595 virq = irq_find_mapping(domain, pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2597 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", in rzg2l_gpio_irq_restore()
2598 pctrl->hwirq[i]); in rzg2l_gpio_irq_restore()
2604 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2612 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2616 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_irq_restore()
2619 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); in rzg2l_gpio_irq_restore()
2631 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); in rzg2l_gpio_irq_domain_free() local
2637 if (pctrl->hwirq[i] == hwirq) { in rzg2l_gpio_irq_domain_free()
2638 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); in rzg2l_gpio_irq_domain_free()
2640 spin_lock_irqsave(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2641 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); in rzg2l_gpio_irq_domain_free()
2642 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); in rzg2l_gpio_irq_domain_free()
2643 pctrl->hwirq[i] = 0; in rzg2l_gpio_irq_domain_free()
2655 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); in rzg2l_init_irq_valid_mask() local
2656 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_init_irq_valid_mask()
2666 if (port >= pctrl->data->n_ports || in rzg2l_init_irq_valid_mask()
2668 pctrl->data->port_pin_configs[port]))) in rzg2l_init_irq_valid_mask()
2673 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_reg_cache_alloc() argument
2675 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_reg_cache_alloc()
2678 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2682 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2686 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2690 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2694 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2698 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); in rzg2l_pinctrl_reg_cache_alloc()
2703 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_reg_cache_alloc()
2705 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), in rzg2l_pinctrl_reg_cache_alloc()
2710 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), in rzg2l_pinctrl_reg_cache_alloc()
2716 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2722 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, in rzg2l_pinctrl_reg_cache_alloc()
2729 pctrl->cache = cache; in rzg2l_pinctrl_reg_cache_alloc()
2730 pctrl->dedicated_cache = dedicated_cache; in rzg2l_pinctrl_reg_cache_alloc()
2735 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_register() argument
2737 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
2738 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
2739 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
2757 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
2762 of_args.args[2] != pctrl->data->n_port_pins) in rzg2l_gpio_register()
2763 return dev_err_probe(pctrl->dev, -EINVAL, in rzg2l_gpio_register()
2766 chip->names = pctrl->data->port_pins; in rzg2l_gpio_register()
2775 chip->parent = pctrl->dev; in rzg2l_gpio_register()
2782 girq->fwnode = dev_fwnode(pctrl->dev); in rzg2l_gpio_register()
2789 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
2790 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
2791 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
2792 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
2793 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
2794 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
2795 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
2797 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
2799 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
2804 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_register() argument
2806 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_register()
2812 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
2813 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
2814 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
2815 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
2816 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
2817 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
2818 if (pctrl->data->num_custom_params) { in rzg2l_pinctrl_register()
2819 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; in rzg2l_pinctrl_register()
2820 pctrl->desc.custom_params = pctrl->data->custom_params; in rzg2l_pinctrl_register()
2822 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; in rzg2l_pinctrl_register()
2826 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
2830 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
2835 pctrl->pins = pins; in rzg2l_pinctrl_register()
2836 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
2838 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
2840 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
2843 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
2845 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, in rzg2l_pinctrl_register()
2852 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
2853 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
2856 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
2857 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
2861 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), in rzg2l_pinctrl_register()
2863 if (!pctrl->settings) in rzg2l_pinctrl_register()
2866 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { in rzg2l_pinctrl_register()
2868 pctrl->settings[i].power_source = 3300; in rzg2l_pinctrl_register()
2870 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); in rzg2l_pinctrl_register()
2873 pctrl->settings[i].power_source = ret; in rzg2l_pinctrl_register()
2877 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); in rzg2l_pinctrl_register()
2881 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
2882 &pctrl->pctl); in rzg2l_pinctrl_register()
2884 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
2886 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
2888 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
2890 ret = rzg2l_gpio_register(pctrl); in rzg2l_pinctrl_register()
2892 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); in rzg2l_pinctrl_register()
2899 struct rzg2l_pinctrl *pctrl; in rzg2l_pinctrl_probe() local
2917 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
2918 if (!pctrl) in rzg2l_pinctrl_probe()
2921 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
2923 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
2924 if (!pctrl->data) in rzg2l_pinctrl_probe()
2927 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
2928 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
2929 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
2931 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
2932 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
2933 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), in rzg2l_pinctrl_probe()
2937 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
2938 spin_lock_init(&pctrl->bitmap_lock); in rzg2l_pinctrl_probe()
2939 mutex_init(&pctrl->mutex); in rzg2l_pinctrl_probe()
2940 atomic_set(&pctrl->wakeup_path, 0); in rzg2l_pinctrl_probe()
2942 platform_set_drvdata(pdev, pctrl); in rzg2l_pinctrl_probe()
2944 ret = rzg2l_pinctrl_register(pctrl); in rzg2l_pinctrl_probe()
2948 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()
2952 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) in rzg2l_pinctrl_pm_setup_regs() argument
2954 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_regs()
2955 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_regs()
2963 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_regs()
2972 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); in rzg2l_pinctrl_pm_setup_regs()
2978 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); in rzg2l_pinctrl_pm_setup_regs()
2980 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_regs()
2983 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
2988 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); in rzg2l_pinctrl_pm_setup_regs()
2989 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); in rzg2l_pinctrl_pm_setup_regs()
2992 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_regs()
2995 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_regs()
3002 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) in rzg2l_pinctrl_pm_setup_dedicated_regs() argument
3004 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3009 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same in rzg2l_pinctrl_pm_setup_dedicated_regs()
3012 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3018 cfg = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3020 if (i + 1 < pctrl->data->n_dedicated_pins) { in rzg2l_pinctrl_pm_setup_dedicated_regs()
3021 next_cfg = pctrl->data->dedicated_pins[i + 1].config; in rzg2l_pinctrl_pm_setup_dedicated_regs()
3037 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3041 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), in rzg2l_pinctrl_pm_setup_dedicated_regs()
3048 pctrl->base + IOLH(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3053 pctrl->base + IEN(off) + 4, in rzg2l_pinctrl_pm_setup_dedicated_regs()
3061 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_pm_setup_pfc() argument
3063 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; in rzg2l_pinctrl_pm_setup_pfc()
3066 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3067 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); in rzg2l_pinctrl_pm_setup_pfc()
3078 cfg = pctrl->data->port_pin_configs[port]; in rzg2l_pinctrl_pm_setup_pfc()
3083 pm = readw(pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3085 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_pm_setup_pfc()
3093 writew(pm, pctrl->base + PM(off)); in rzg2l_pinctrl_pm_setup_pfc()
3097 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3102 writel(pfc, pctrl->base + PFC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3106 writeb(pmc, pctrl->base + PMC(off)); in rzg2l_pinctrl_pm_setup_pfc()
3110 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); in rzg2l_pinctrl_pm_setup_pfc()
3111 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pm_setup_pfc()
3116 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); in rzg2l_pinctrl_suspend_noirq() local
3117 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_suspend_noirq()
3119 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_suspend_noirq()
3121 rzg2l_pinctrl_pm_setup_regs(pctrl, true); in rzg2l_pinctrl_suspend_noirq()
3122 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); in rzg2l_pinctrl_suspend_noirq()
3126 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_suspend_noirq()
3128 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_suspend_noirq()
3131 cache->qspi = readb(pctrl->base + QSPI); in rzg2l_pinctrl_suspend_noirq()
3132 cache->eth_mode = readb(pctrl->base + ETH_MODE); in rzg2l_pinctrl_suspend_noirq()
3134 if (!atomic_read(&pctrl->wakeup_path)) in rzg2l_pinctrl_suspend_noirq()
3135 clk_disable_unprepare(pctrl->clk); in rzg2l_pinctrl_suspend_noirq()
3144 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); in rzg2l_pinctrl_resume_noirq() local
3145 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; in rzg2l_pinctrl_resume_noirq()
3147 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; in rzg2l_pinctrl_resume_noirq()
3150 if (!atomic_read(&pctrl->wakeup_path)) { in rzg2l_pinctrl_resume_noirq()
3151 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_resume_noirq()
3156 writeb(cache->qspi, pctrl->base + QSPI); in rzg2l_pinctrl_resume_noirq()
3157 writeb(cache->eth_mode, pctrl->base + ETH_MODE); in rzg2l_pinctrl_resume_noirq()
3160 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); in rzg2l_pinctrl_resume_noirq()
3162 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); in rzg2l_pinctrl_resume_noirq()
3165 rzg2l_pinctrl_pm_setup_pfc(pctrl); in rzg2l_pinctrl_resume_noirq()
3166 rzg2l_pinctrl_pm_setup_regs(pctrl, false); in rzg2l_pinctrl_resume_noirq()
3167 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); in rzg2l_pinctrl_resume_noirq()
3168 rzg2l_gpio_irq_restore(pctrl); in rzg2l_pinctrl_resume_noirq()
3173 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) in rzg2l_pwpr_pfc_lock_unlock() argument
3175 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzg2l_pwpr_pfc_lock_unlock()
3179 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3180 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3183 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ in rzg2l_pwpr_pfc_lock_unlock()
3184 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ in rzg2l_pwpr_pfc_lock_unlock()
3188 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) in rzv2h_pwpr_pfc_lock_unlock() argument
3190 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; in rzv2h_pwpr_pfc_lock_unlock()
3195 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3196 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3199 pwpr = readb(pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()
3200 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); in rzv2h_pwpr_pfc_lock_unlock()