22 static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_ana_fifo_en()  argument
25 	mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);  in mtk_hdmi_ana_fifo_en()
29 mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable)  in mtk_phy_tmds_clk_ratio()  argument
31 	void __iomem *regs = hdmi_phy->regs;  in mtk_phy_tmds_clk_ratio()
33 	mtk_hdmi_ana_fifo_en(hdmi_phy);  in mtk_phy_tmds_clk_ratio()
46 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_sel_src()  local
47 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_sel_src()
58 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_perf()  local
59 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_perf()
91 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_set_hw()  local
92 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_set_hw()
211 static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,  in mtk_hdmi_pll_calc()  argument
227 		hdmi_phy->tmds_over_340M = true;  in mtk_hdmi_pll_calc()
229 		hdmi_phy->tmds_over_340M = false;  in mtk_hdmi_pll_calc()
304 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_drv_setting()  local
305 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_drv_setting()
309 	u32 pixel_clk = hdmi_phy->pll_rate;  in mtk_hdmi_pll_drv_setting()
361 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_prepare()  local
362 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_prepare()
395 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_unprepare()  local
396 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_unprepare()
413 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_set_rate()  local
415 	dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate,  in mtk_hdmi_pll_set_rate()
418 	return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate);  in mtk_hdmi_pll_set_rate()
424 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_round_rate()  local
426 	hdmi_phy->pll_rate = rate;  in mtk_hdmi_pll_round_rate()
433 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_recalc_rate()  local
435 	return hdmi_phy->pll_rate;  in mtk_hdmi_pll_recalc_rate()
446 static void vtx_signal_en(struct mtk_hdmi_phy *hdmi_phy, bool on)  in vtx_signal_en()  argument
448 	void __iomem *regs = hdmi_phy->regs;  in vtx_signal_en()
456 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_phy_enable_tmds()  argument
458 	vtx_signal_en(hdmi_phy, true);  in mtk_hdmi_phy_enable_tmds()
462 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_phy_disable_tmds()  argument
464 	vtx_signal_en(hdmi_phy, false);  in mtk_hdmi_phy_disable_tmds()
470 	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);  in mtk_hdmi_phy_configure()  local
473 	ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);  in mtk_hdmi_phy_configure()
478 	mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M);  in mtk_hdmi_phy_configure()
485 	struct mtk_hdmi_phy *hdmi_phy = rdev_get_drvdata(rdev);  in mtk_hdmi_phy_pwr5v_enable()  local
487 	mtk_phy_set_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O);  in mtk_hdmi_phy_pwr5v_enable()
494 	struct mtk_hdmi_phy *hdmi_phy = rdev_get_drvdata(rdev);  in mtk_hdmi_phy_pwr5v_disable()  local
496 	mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CTL_1, RG_HDMITX_PWR5V_O);  in mtk_hdmi_phy_pwr5v_disable()
503 	struct mtk_hdmi_phy *hdmi_phy = rdev_get_drvdata(rdev);  in mtk_hdmi_phy_pwr5v_is_enabled()  local
505 	return !!(readl(hdmi_phy->regs + HDMI_CTL_1) & RG_HDMITX_PWR5V_O);  in mtk_hdmi_phy_pwr5v_is_enabled()