Lines Matching +full:1 +full:g
21 TARGET_ANA_AC = 1,
71 #define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
72 #define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
78 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\
79 0, 1, 4)
81 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1)
95 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\
105 #define ANA_AC_PROBE_CFG(g) \ argument
106 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \
107 32, 0, 0, 1, 4)
139 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0)
146 #define ANA_AC_PROBE_PORT_CFG(g) \ argument
147 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \
148 32, 8, 0, 1, 4)
152 #define ANA_AC_PROBE_PORT_CFG1(g) \ argument
153 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \
154 32, 12, 0, 1, 4)
158 #define ANA_AC_PROBE_PORT_CFG2(g) \ argument
159 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \
160 32, 16, 0, 1, 4)
169 #define ANA_AC_SRC_CFG(g) \ argument
170 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \
171 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4)
175 #define ANA_AC_SRC_CFG1(g) \ argument
176 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \
177 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4)
181 #define ANA_AC_SRC_CFG2(g) \ argument
182 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \
183 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4)
192 #define ANA_AC_PGID_CFG(g) \ argument
193 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \
194 regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4)
198 #define ANA_AC_PGID_CFG1(g) \ argument
199 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \
200 regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4)
204 #define ANA_AC_PGID_CFG2(g) \ argument
205 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \
206 regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4)
215 #define ANA_AC_PGID_MISC_CFG(g) \ argument
216 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \
217 regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4)
225 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1)
239 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0, \
240 0, 1, 4)
249 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0)
256 #define ANA_AC_TSN_SF_CFG(g) \ argument
257 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g, \
258 regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4)
261 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16)
273 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1)
287 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \
288 16, 0, 0, 1, 4)
303 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1)
317 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \
318 0, 0, 1, 4)
321 GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0)
335 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \
336 8, 0, 1, 4)
352 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
353 48, 0, 1, 4)
357 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
358 52, 0, 1, 4)
362 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
363 56, 0, 1, 4)
421 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
422 60, 0, 1, 4)
426 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
427 64, 0, 1, 4)
431 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
448 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
453 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
458 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
459 0, 0, 1, 4)
463 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
464 4, 0, 1, 4)
468 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
469 8, 0, 1, 4)
503 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
504 12, 0, 1, 4)
508 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\
509 0, 1, 20, 0, r, 4, 4)
512 GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0)
520 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\
521 0, 1, 20, 16, 0, 1, 4)
530 #define ANA_AC_PORT_STAT_CFG(g, r) \ argument
531 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\
540 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1)
553 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) \ argument
554 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\
559 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
560 0, 1, 24, 0, r, 2, 4)
570 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
571 0, 1, 24, 8, r, 2, 4)
581 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
582 0, 1, 24, 16, r, 2, 4)
592 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
681 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
682 412, 0, 1, 4)
702 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1)
716 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
733 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
734 440, 0, 1, 4)
756 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
766 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) \ argument
767 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g, \
806 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1)
819 #define ANA_ACL_CNT_A(g) \ argument
820 __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0, \
821 0, 1, 4)
824 #define ANA_ACL_CNT_B(g) \ argument
825 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g, \
826 regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4)
830 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16, \
929 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1)
943 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \
944 0, 1, 1160, 1148, 0, 1, 4)
954 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \
955 0, 1, 8, 0, 0, 1, 4)
969 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1)
983 __REG(TARGET_ANA_AC_POL, 0, 1, \
984 regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4)
998 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1)
1011 #define ANA_AC_SDLB_XLB_START(g) \ argument
1012 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1013 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4)
1016 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0)
1023 #define ANA_AC_SDLB_PUP_INTERVAL(g) \ argument
1024 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1025 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4)
1034 #define ANA_AC_SDLB_PUP_CTRL(g) \ argument
1035 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1036 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4)
1051 #define ANA_AC_SDLB_LBGRP_MISC(g) \ argument
1052 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1053 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4)
1056 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8)
1063 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ argument
1064 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1065 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4)
1074 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ argument
1075 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1076 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4)
1084 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1)
1091 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16)
1098 #define ANA_AC_SDLB_PUP_TOKENS(g, r) \ argument
1099 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1109 #define ANA_AC_SDLB_THRES(g, r) \ argument
1110 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1126 #define ANA_AC_SDLB_XLB_NEXT(g) \ argument
1127 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1128 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4)
1131 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0)
1138 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24)
1145 #define ANA_AC_SDLB_INH_CTRL(g, r) \ argument
1146 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1168 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ argument
1169 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1170 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4)
1173 GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0)
1180 #define ANA_AC_SDLB_DLB_MISC(g) \ argument
1181 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1182 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4)
1203 #define ANA_AC_SDLB_DLB_CFG(g) \ argument
1204 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \
1205 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4)
1249 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0)
1256 #define ANA_CL_FILTER_CTRL(g) \ argument
1257 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1258 regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4)
1266 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1)
1279 #define ANA_CL_VLAN_FILTER_CTRL(g, r) \ argument
1280 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1337 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1)
1350 #define ANA_CL_ETAG_FILTER_CTRL(g) \ argument
1351 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1352 regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4)
1354 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
1367 #define ANA_CL_VLAN_CTRL(g) \ argument
1368 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1369 regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4)
1438 #define ANA_CL_VLAN_CTRL_2(g) \ argument
1439 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1440 regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4)
1442 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0)
1449 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) \ argument
1450 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1466 #define ANA_CL_QOS_CFG(g) \ argument
1467 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1468 regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4)
1543 #define ANA_CL_CAPTURE_BPDU_CFG(g) \ argument
1544 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1545 regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4)
1548 #define ANA_CL_ADV_CL_CFG_2(g, r) \ argument
1549 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1552 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1)
1565 #define ANA_CL_ADV_CL_CFG(g, r) \ argument
1566 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \
1599 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1)
1613 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\
1624 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \
1645 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1)
1659 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \
1670 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \
1671 regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4)
1733 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1)
1747 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \
1748 regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4)
1753 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \
1754 regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4)
1759 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \
1760 regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4)
1770 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \
1781 #define ANA_L2_DLB_CFG(g) \ argument
1782 __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \
1783 0, 1, 4)
1786 GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0)
1793 #define ANA_L2_TSN_CFG(g) \ argument
1794 __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \
1795 0, 1, 4)
1798 GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0)
1806 __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\
1807 0, 1, 4)
1816 #define ANA_L3_VLAN_CFG(g) \ argument
1817 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \
1818 1, 4)
1862 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1)
1875 #define ANA_L3_VLAN_MASK_CFG(g) \ argument
1876 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\
1877 1, 4)
1881 #define ANA_L3_VLAN_MASK_CFG1(g) \ argument
1882 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\
1883 1, 4)
1887 #define ANA_L3_VLAN_MASK_CFG2(g) \ argument
1888 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\
1889 1, 4)
1898 #define ASM_RX_IN_BYTES_CNT(g) \ argument
1899 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1900 0, 0, 1, 4)
1903 #define ASM_RX_SYMBOL_ERR_CNT(g) \ argument
1904 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1905 4, 0, 1, 4)
1908 #define ASM_RX_PAUSE_CNT(g) \ argument
1909 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1910 8, 0, 1, 4)
1913 #define ASM_RX_UNSUP_OPCODE_CNT(g) \ argument
1914 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1915 12, 0, 1, 4)
1918 #define ASM_RX_OK_BYTES_CNT(g) \ argument
1919 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1920 16, 0, 1, 4)
1923 #define ASM_RX_BAD_BYTES_CNT(g) \ argument
1924 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1925 20, 0, 1, 4)
1928 #define ASM_RX_UC_CNT(g) \ argument
1929 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1930 24, 0, 1, 4)
1933 #define ASM_RX_MC_CNT(g) \ argument
1934 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1935 28, 0, 1, 4)
1938 #define ASM_RX_BC_CNT(g) \ argument
1939 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1940 32, 0, 1, 4)
1943 #define ASM_RX_CRC_ERR_CNT(g) \ argument
1944 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1945 36, 0, 1, 4)
1948 #define ASM_RX_UNDERSIZE_CNT(g) \ argument
1949 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1950 40, 0, 1, 4)
1953 #define ASM_RX_FRAGMENTS_CNT(g) \ argument
1954 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1955 44, 0, 1, 4)
1958 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) \ argument
1959 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1960 48, 0, 1, 4)
1963 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ argument
1964 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1965 52, 0, 1, 4)
1968 #define ASM_RX_OVERSIZE_CNT(g) \ argument
1969 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1970 56, 0, 1, 4)
1973 #define ASM_RX_JABBERS_CNT(g) \ argument
1974 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1975 60, 0, 1, 4)
1978 #define ASM_RX_SIZE64_CNT(g) \ argument
1979 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1980 64, 0, 1, 4)
1983 #define ASM_RX_SIZE65TO127_CNT(g) \ argument
1984 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1985 68, 0, 1, 4)
1988 #define ASM_RX_SIZE128TO255_CNT(g) \ argument
1989 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1990 72, 0, 1, 4)
1993 #define ASM_RX_SIZE256TO511_CNT(g) \ argument
1994 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
1995 76, 0, 1, 4)
1998 #define ASM_RX_SIZE512TO1023_CNT(g) \ argument
1999 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2000 80, 0, 1, 4)
2003 #define ASM_RX_SIZE1024TO1518_CNT(g) \ argument
2004 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2005 84, 0, 1, 4)
2008 #define ASM_RX_SIZE1519TOMAX_CNT(g) \ argument
2009 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2010 88, 0, 1, 4)
2013 #define ASM_RX_IPG_SHRINK_CNT(g) \ argument
2014 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2015 92, 0, 1, 4)
2018 #define ASM_TX_OUT_BYTES_CNT(g) \ argument
2019 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2020 96, 0, 1, 4)
2023 #define ASM_TX_PAUSE_CNT(g) \ argument
2024 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2025 100, 0, 1, 4)
2028 #define ASM_TX_OK_BYTES_CNT(g) \ argument
2029 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2030 104, 0, 1, 4)
2033 #define ASM_TX_UC_CNT(g) \ argument
2034 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2035 108, 0, 1, 4)
2038 #define ASM_TX_MC_CNT(g) \ argument
2039 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2040 112, 0, 1, 4)
2043 #define ASM_TX_BC_CNT(g) \ argument
2044 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2045 116, 0, 1, 4)
2048 #define ASM_TX_SIZE64_CNT(g) \ argument
2049 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2050 120, 0, 1, 4)
2053 #define ASM_TX_SIZE65TO127_CNT(g) \ argument
2054 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2055 124, 0, 1, 4)
2058 #define ASM_TX_SIZE128TO255_CNT(g) \ argument
2059 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2060 128, 0, 1, 4)
2063 #define ASM_TX_SIZE256TO511_CNT(g) \ argument
2064 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2065 132, 0, 1, 4)
2068 #define ASM_TX_SIZE512TO1023_CNT(g) \ argument
2069 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2070 136, 0, 1, 4)
2073 #define ASM_TX_SIZE1024TO1518_CNT(g) \ argument
2074 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2075 140, 0, 1, 4)
2078 #define ASM_TX_SIZE1519TOMAX_CNT(g) \ argument
2079 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2080 144, 0, 1, 4)
2083 #define ASM_RX_ALIGNMENT_LOST_CNT(g) \ argument
2084 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2085 148, 0, 1, 4)
2088 #define ASM_RX_TAGGED_FRMS_CNT(g) \ argument
2089 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2090 152, 0, 1, 4)
2093 #define ASM_RX_UNTAGGED_FRMS_CNT(g) \ argument
2094 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2095 156, 0, 1, 4)
2098 #define ASM_TX_TAGGED_FRMS_CNT(g) \ argument
2099 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2100 160, 0, 1, 4)
2103 #define ASM_TX_UNTAGGED_FRMS_CNT(g) \ argument
2104 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2105 164, 0, 1, 4)
2108 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) \ argument
2109 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2110 168, 0, 1, 4)
2113 #define ASM_PMAC_RX_PAUSE_CNT(g) \ argument
2114 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2115 172, 0, 1, 4)
2118 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) \ argument
2119 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2120 176, 0, 1, 4)
2123 #define ASM_PMAC_RX_OK_BYTES_CNT(g) \ argument
2124 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2125 180, 0, 1, 4)
2128 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) \ argument
2129 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2130 184, 0, 1, 4)
2133 #define ASM_PMAC_RX_UC_CNT(g) \ argument
2134 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2135 188, 0, 1, 4)
2138 #define ASM_PMAC_RX_MC_CNT(g) \ argument
2139 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2140 192, 0, 1, 4)
2143 #define ASM_PMAC_RX_BC_CNT(g) \ argument
2144 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2145 196, 0, 1, 4)
2148 #define ASM_PMAC_RX_CRC_ERR_CNT(g) \ argument
2149 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2150 200, 0, 1, 4)
2153 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) \ argument
2154 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2155 204, 0, 1, 4)
2158 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) \ argument
2159 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2160 208, 0, 1, 4)
2163 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) \ argument
2164 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2165 212, 0, 1, 4)
2168 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ argument
2169 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2170 216, 0, 1, 4)
2173 #define ASM_PMAC_RX_OVERSIZE_CNT(g) \ argument
2174 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2175 220, 0, 1, 4)
2178 #define ASM_PMAC_RX_JABBERS_CNT(g) \ argument
2179 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2180 224, 0, 1, 4)
2183 #define ASM_PMAC_RX_SIZE64_CNT(g) \ argument
2184 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2185 228, 0, 1, 4)
2188 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) \ argument
2189 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2190 232, 0, 1, 4)
2193 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) \ argument
2194 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2195 236, 0, 1, 4)
2198 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) \ argument
2199 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2200 240, 0, 1, 4)
2203 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) \ argument
2204 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2205 244, 0, 1, 4)
2208 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) \ argument
2209 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2210 248, 0, 1, 4)
2213 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) \ argument
2214 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2215 252, 0, 1, 4)
2218 #define ASM_PMAC_TX_PAUSE_CNT(g) \ argument
2219 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2220 256, 0, 1, 4)
2223 #define ASM_PMAC_TX_OK_BYTES_CNT(g) \ argument
2224 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2225 260, 0, 1, 4)
2228 #define ASM_PMAC_TX_UC_CNT(g) \ argument
2229 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2230 264, 0, 1, 4)
2233 #define ASM_PMAC_TX_MC_CNT(g) \ argument
2234 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2235 268, 0, 1, 4)
2238 #define ASM_PMAC_TX_BC_CNT(g) \ argument
2239 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2240 272, 0, 1, 4)
2243 #define ASM_PMAC_TX_SIZE64_CNT(g) \ argument
2244 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2245 276, 0, 1, 4)
2248 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) \ argument
2249 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2250 280, 0, 1, 4)
2253 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) \ argument
2254 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2255 284, 0, 1, 4)
2258 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) \ argument
2259 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2260 288, 0, 1, 4)
2263 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) \ argument
2264 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2265 292, 0, 1, 4)
2268 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) \ argument
2269 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2270 296, 0, 1, 4)
2273 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) \ argument
2274 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2275 300, 0, 1, 4)
2278 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) \ argument
2279 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2280 304, 0, 1, 4)
2283 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) \ argument
2284 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2285 308, 0, 1, 4)
2288 #define ASM_MM_RX_SMD_ERR_CNT(g) \ argument
2289 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2290 312, 0, 1, 4)
2293 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) \ argument
2294 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2295 316, 0, 1, 4)
2298 #define ASM_MM_RX_MERGE_FRAG_CNT(g) \ argument
2299 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2300 320, 0, 1, 4)
2303 #define ASM_MM_TX_PFRAGMENT_CNT(g) \ argument
2304 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2305 324, 0, 1, 4)
2308 #define ASM_TX_MULTI_COLL_CNT(g) \ argument
2309 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2310 328, 0, 1, 4)
2313 #define ASM_TX_LATE_COLL_CNT(g) \ argument
2314 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2315 332, 0, 1, 4)
2318 #define ASM_TX_XCOLL_CNT(g) \ argument
2319 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2320 336, 0, 1, 4)
2323 #define ASM_TX_DEFER_CNT(g) \ argument
2324 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2325 340, 0, 1, 4)
2328 #define ASM_TX_XDEFER_CNT(g) \ argument
2329 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2330 344, 0, 1, 4)
2333 #define ASM_TX_BACKOFF1_CNT(g) \ argument
2334 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2335 348, 0, 1, 4)
2338 #define ASM_TX_CSENSE_CNT(g) \ argument
2339 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2340 352, 0, 1, 4)
2343 #define ASM_RX_IN_BYTES_MSB_CNT(g) \ argument
2344 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2345 356, 0, 1, 4)
2354 #define ASM_RX_OK_BYTES_MSB_CNT(g) \ argument
2355 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2356 360, 0, 1, 4)
2365 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) \ argument
2366 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2367 364, 0, 1, 4)
2376 #define ASM_RX_BAD_BYTES_MSB_CNT(g) \ argument
2377 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2378 368, 0, 1, 4)
2387 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) \ argument
2388 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2389 372, 0, 1, 4)
2398 #define ASM_TX_OUT_BYTES_MSB_CNT(g) \ argument
2399 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2400 376, 0, 1, 4)
2409 #define ASM_TX_OK_BYTES_MSB_CNT(g) \ argument
2410 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2411 380, 0, 1, 4)
2420 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) \ argument
2421 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2422 384, 0, 1, 4)
2431 #define ASM_RX_SYNC_LOST_ERR_CNT(g) \ argument
2432 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \
2433 388, 0, 1, 4)
2437 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \
2438 regs->gsize[GW_ASM_CFG], 0, 0, 1, 4)
2448 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \
2505 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1)
2519 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\
2522 #define ASM_RAM_INIT_RAM_INIT BIT(1)
2537 __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
2577 __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS], \
2578 regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4)
2672 #define DEV2G5_PHAD_CTRL(t, g) \ argument
2673 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \
2674 regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
2691 #define DEV2G5_PHAD_CTRL(t, g) \ argument
2692 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \
2693 regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
2711 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \
2728 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1, \
2745 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \
2748 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0)
2756 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \
2773 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \
2820 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \
2841 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
2855 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\
2914 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \
2915 1, 4)
2919 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\
2931 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
2948 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
2965 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
3012 __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
3071 __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
3082 __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
3104 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1, \
3157 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \
3174 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \
3197 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \
3208 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\
3223 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
3237 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\
3254 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\
3265 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\
3294 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\
3329 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \
3338 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
3352 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \
3361 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1)
3375 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \
3398 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\
3413 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
3427 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\
3436 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
3450 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\
3479 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\
3508 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\
3525 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \
3594 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
3608 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \
3647 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
3661 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4)
3677 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4)
3693 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1, \
3740 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1, \
3745 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1, \
3750 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1, \
3755 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \
3760 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \
3765 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \
3770 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \
3775 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \
3780 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \
3785 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \
3790 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \
3795 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \
3800 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \
3805 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \
3810 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \
3815 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \
3820 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \
3825 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \
3830 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \
3835 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \
3840 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \
3845 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \
3850 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \
3855 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \
3860 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \
3865 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\
3870 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\
3875 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\
3880 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\
3885 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\
3890 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\
3895 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\
3900 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\
3905 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\
3910 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\
3915 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\
3920 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\
3925 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\
3930 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\
3935 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\
3940 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\
3945 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\
3950 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\
3955 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\
3960 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\
3965 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\
3970 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\
3975 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\
3980 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\
3985 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\
3990 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\
3995 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\
4000 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\
4005 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\
4010 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\
4015 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\
4020 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\
4025 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\
4030 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\
4035 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\
4040 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\
4045 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\
4050 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\
4055 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\
4060 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\
4065 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\
4070 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\
4075 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\
4080 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\
4085 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\
4090 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\
4095 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\
4100 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\
4105 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\
4110 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\
4115 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\
4120 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\
4125 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\
4130 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1, \
4135 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1, \
4146 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1, \
4151 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \
4162 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \
4167 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \
4178 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \
4183 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \
4194 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \
4199 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \
4210 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \
4215 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \
4226 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \
4231 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \
4242 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \
4247 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \
4258 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1, \
4317 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \
4322 __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
4324 #define DSM_RAM_INIT_RAM_INIT BIT(1)
4338 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, \
4367 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \
4382 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1)
4396 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, \
4399 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1)
4413 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, \
4428 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1)
4442 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, \
4453 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, \
4464 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, \
4485 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)
4519 #define EACL_VCAP_ES2_KEY_SEL(g, r) \ argument
4520 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \
4521 g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4)
4535 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1)
4548 #define EACL_ES2_CNT(g) \ argument
4549 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g, \
4550 regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4)
4554 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \
4555 0, 1, 4)
4581 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1)
4595 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0, \
4634 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1)
4648 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \
4649 1, 4)
4651 #define EACL_RAM_INIT_RAM_INIT BIT(1)
4665 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1, \
4676 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1, \
4687 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1, \
4698 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \
4703 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \
4708 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\
4713 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\
4718 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\
4743 GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1)
4757 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\
4768 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\
4785 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\
4806 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1)
4820 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\
4831 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\
4842 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\
4853 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\
4864 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\
4881 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\
4934 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\
4937 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0)
4945 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\
4956 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0, \
4957 1, 4)
4971 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1)
4985 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \
4986 regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4)
4995 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1)
5010 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \
5011 1, 4)
5013 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1)
5027 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \
5032 GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0)
5039 #define GCB_SIO_CLOCK(g) \ argument
5040 __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g, \
5041 regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4)
5056 #define HSCH_CIR_CFG(g) \ argument
5057 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \
5058 1, 4)
5073 #define HSCH_EIR_CFG(g) \ argument
5074 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \
5075 1, 4)
5090 #define HSCH_SE_CFG(g) \ argument
5091 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \
5092 1, 4)
5095 GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6)
5113 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1)
5126 #define HSCH_SE_CONNECT(g) \ argument
5127 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\
5128 1, 4)
5131 GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0)
5138 #define HSCH_SE_DLB_SENSE(g) \ argument
5139 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\
5140 1, 4)
5149 GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3)
5161 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1)
5174 #define HSCH_DWRR_ENTRY(g) \ argument
5175 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g, \
5176 regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4)
5192 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \
5193 284, 0, 1, 4)
5196 GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14)
5217 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \
5218 640, 0, 1, 4)
5227 #define HSCH_HSCH_TIMER_CFG(g, r) \ argument
5228 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \
5238 #define HSCH_HSCH_LEAK_CFG(g, r) \ argument
5239 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \
5243 GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1)
5257 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \
5258 1, 4)
5279 GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18)
5298 GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0)
5306 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \
5327 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1)
5341 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288, \
5352 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \
5363 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1, \
5364 regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4)
5374 #define HSIO_WRAP_XMII_CFG(g) \ argument
5375 __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 0, 0, 1, 4)
5377 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1)
5385 #define HSIO_WRAP_RGMII_CFG(g) \ argument
5386 __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 4, 0, 1, 4)
5394 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST BIT(1)
5408 #define HSIO_WRAP_DLL_CFG(g, r) \ argument
5409 __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 12, r, 2, 4)
5437 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
5452 GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5)
5458 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)
5472 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
5488 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
5492 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
5568 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
5571 GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0)
5579 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
5659 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1)
5673 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
5689 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
5705 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
5737 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
5751 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
5754 GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4)
5769 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
5834 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
5851 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
5856 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
5873 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
5878 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
5883 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
5885 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
5899 __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0, \
5900 0, 1, 4)
5976 __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4, \
5977 0, 1, 4)
6000 __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
6077 __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
6099 __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \
6100 1, 4)
6176 __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \
6177 1, 4)
6199 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
6209 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1)
6293 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
6302 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1)
6381 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
6389 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1)
6433 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
6441 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1)
6515 #define PORT_CONF_USGMII_CFG(g) \ argument
6516 __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
6554 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1)
6562 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\
6566 GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0)
6574 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\
6578 GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0)
6586 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\
6590 GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0)
6598 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0, \
6599 1, 4)
6626 #define PTP_CLK_PER_CFG(g, r) \ argument
6627 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6631 #define PTP_PTP_CUR_NSEC(g) \ argument
6632 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6633 8, 0, 1, 4)
6642 #define PTP_PTP_CUR_NSEC_FRAC(g) \ argument
6643 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6644 12, 0, 1, 4)
6653 #define PTP_PTP_CUR_SEC_LSB(g) \ argument
6654 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6655 16, 0, 1, 4)
6658 #define PTP_PTP_CUR_SEC_MSB(g) \ argument
6659 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6660 20, 0, 1, 4)
6669 #define PTP_NTP_CUR_NSEC(g) \ argument
6670 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6671 24, 0, 1, 4)
6674 #define PTP_PTP_PIN_CFG(g) \ argument
6675 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\
6686 …GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYN…
6700 GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21)
6737 #define PTP_PTP_TOD_SEC_MSB(g) \ argument
6738 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\
6748 #define PTP_PTP_TOD_SEC_LSB(g) \ argument
6749 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\
6753 #define PTP_PTP_TOD_NSEC(g) \ argument
6754 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0, \
6755 1, 4)
6764 #define PTP_PTP_TOD_NSEC_FRAC(g) \ argument
6765 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0, \
6766 1, 4)
6775 #define PTP_NTP_NSEC(g) \ argument
6776 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0, \
6777 1, 4)
6780 #define PTP_PIN_WF_HIGH_PERIOD(g) \ argument
6781 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0, \
6782 1, 4)
6791 #define PTP_PIN_WF_LOW_PERIOD(g) \ argument
6792 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0, \
6793 1, 4)
6802 #define PTP_PIN_IOBOUNCH_DELAY(g) \ argument
6803 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0, \
6804 1, 4)
6819 #define PTP_PHAD_CTRL(g) \ argument
6820 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \
6822 regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
6852 #define PTP_PHAD_CYC_STAT(g) \ argument
6853 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \
6855 regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4)
6860 __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4)
6886 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
6901 __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4)
6912 __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4)
6922 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \
6967 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1)
6981 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4)
6984 GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6)
6991 #define QRES_RES_CFG(g) \ argument
6992 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
6995 GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0)
7002 #define QRES_RES_STAT(g) \ argument
7003 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
7006 GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0)
7013 #define QRES_RES_STAT_CUR(g) \ argument
7014 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
7017 GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0)
7025 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
7033 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
7047 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
7051 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
7053 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
7061 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
7063 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0)
7071 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
7087 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
7091 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
7125 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
7139 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0)
7147 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \
7151 GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14)
7158 GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2)
7164 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1)
7178 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \
7182 GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0)
7190 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \
7193 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1)
7207 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \
7208 844, 0, 1, 4)
7211 GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0)
7219 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r, \
7230 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \
7231 1, 4)
7239 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1)
7253 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \
7254 1, 4)
7256 #define QSYS_RAM_INIT_RAM_INIT BIT(1)
7270 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r, \
7281 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\
7285 GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3)
7291 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1)
7305 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\
7306 1, 4)
7332 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1)
7345 #define REW_PORT_VLAN_CFG(g) \ argument
7346 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7347 regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4)
7368 #define REW_PCP_MAP_DE0(g, r) \ argument
7369 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7379 #define REW_PCP_MAP_DE1(g, r) \ argument
7380 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7390 #define REW_DEI_MAP_DE0(g, r) \ argument
7391 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7401 #define REW_DEI_MAP_DE1(g, r) \ argument
7402 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7412 #define REW_TAG_CTRL(g) \ argument
7413 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7414 regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4)
7453 #define REW_DSCP_MAP(g) \ argument
7454 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \
7455 regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4)
7457 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1)
7472 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
7498 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
7513 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
7524 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
7535 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
7540 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
7545 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
7556 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
7564 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0)
7572 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\
7575 #define REW_RAM_INIT_RAM_INIT BIT(1)
7589 __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7627 #define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1)
7641 __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7657 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7661 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7665 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7669 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7673 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7677 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7681 __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7691 __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7701 __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7711 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7715 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7719 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7723 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7727 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7731 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7735 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7739 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7743 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7747 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7751 __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7789 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1)
7803 __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7819 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7823 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7827 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7831 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7835 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7839 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7843 __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7853 __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7863 __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7873 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7877 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7881 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7885 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7889 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7893 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7897 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7901 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7905 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7909 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7913 __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7951 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1)
7965 __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7981 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7985 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7989 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7993 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7997 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
8001 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
8005 __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
8015 __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
8025 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
8029 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
8033 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
8037 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
8041 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
8045 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
8049 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
8053 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
8057 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
8061 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
8065 __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
8067 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1)
8081 __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\
8084 #define VOP_RAM_INIT_RAM_INIT BIT(1)
8098 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \
8099 1, 4)
8108 GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5)
8127 #define XQS_QLIMIT_SHR_TOP_CFG(g) \ argument
8128 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\
8129 1, 4)
8132 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0)
8139 #define XQS_QLIMIT_SHR_ATOP_CFG(g) \ argument
8140 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\
8141 1, 4)
8144 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0)
8151 #define XQS_QLIMIT_SHR_CTOP_CFG(g) \ argument
8152 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\
8153 1, 4)
8156 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0)
8163 #define XQS_QLIMIT_SHR_QLIM_CFG(g) \ argument
8164 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12, \
8165 0, 1, 4)
8168 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0)
8175 #define XQS_CNT(g) \ argument
8176 __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)
8181 __REG(TARGET_DEVRGMII, t, 2, 0, 0, 1, 36, 0, 0, 1, 4)
8192 __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 0, 0, 1, 4)
8209 __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4)
8223 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
8238 __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 24, 0, 1, 4)