82 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\  argument
84 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\  argument
88 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
90 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
99 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\  argument
101 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\  argument
110 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\  argument
112 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\  argument
116 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\  argument
118 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\  argument
122 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\  argument
124 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\  argument
128 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\  argument
130 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\  argument
134 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\  argument
136 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\  argument
140 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\  argument
142 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\  argument
163 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\  argument
165 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\  argument
186 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\  argument
188 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\  argument
209 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\  argument
211 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\  argument
220 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\  argument
222 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\  argument
226 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\  argument
228 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\  argument
232 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\  argument
234 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\  argument
243 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\  argument
245 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\  argument
250 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\  argument
252 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\  argument
262 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\  argument
264 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\  argument
268 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\  argument
270 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\  argument
274 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\  argument
276 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\  argument
280 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\  argument
282 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\  argument
291 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\  argument
293 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\  argument
297 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\  argument
299 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\  argument
304 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\  argument
306 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\  argument
310 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\  argument
312 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\  argument
322 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\  argument
324 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\  argument
328 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\  argument
330 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\  argument
339 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\  argument
341 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\  argument
345 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\  argument
347 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\  argument
366 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\  argument
368 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\  argument
372 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\  argument
374 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\  argument
378 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\  argument
380 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\  argument
384 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\  argument
386 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\  argument
390 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\  argument
392 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\  argument
396 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\  argument
398 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\  argument
402 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\  argument
404 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\  argument
408 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\  argument
410 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\  argument
414 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\  argument
416 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\  argument
435 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\  argument
437 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\  argument
441 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\  argument
443 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\  argument
472 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\  argument
474 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\  argument
478 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\  argument
480 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\  argument
484 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\  argument
486 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\  argument
490 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\  argument
492 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\  argument
496 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\  argument
498 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\  argument
513 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\  argument
515 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\  argument
524 #define ANA_AC_STAT_RESET_RESET_SET(x)\  argument
526 #define ANA_AC_STAT_RESET_RESET_GET(x)\  argument
535 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\  argument
537 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\  argument
541 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\  argument
543 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\  argument
547 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\  argument
549 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\  argument
563 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\  argument
565 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\  argument
574 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\  argument
576 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\  argument
585 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\  argument
587 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\  argument
596 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\  argument
598 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\  argument
602 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\  argument
604 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\  argument
608 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\  argument
610 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\  argument
614 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\  argument
616 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\  argument
620 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\  argument
622 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\  argument
626 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\  argument
628 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\  argument
632 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\  argument
634 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\  argument
638 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\  argument
640 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\  argument
644 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\  argument
646 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\  argument
650 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\  argument
652 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\  argument
656 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\  argument
658 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\  argument
662 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\  argument
664 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\  argument
668 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\  argument
670 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\  argument
674 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\  argument
676 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\  argument
685 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\  argument
687 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\  argument
691 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\  argument
693 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\  argument
697 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\  argument
699 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\  argument
703 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\  argument
705 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\  argument
709 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\  argument
711 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\  argument
720 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\  argument
722 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\  argument
726 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\  argument
728 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\  argument
737 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\  argument
739 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\  argument
743 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\  argument
745 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\  argument
749 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\  argument
751 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\  argument
760 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
762 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
771 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\  argument
773 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\  argument
777 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\  argument
779 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\  argument
783 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\  argument
785 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\  argument
789 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\  argument
791 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\  argument
795 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\  argument
797 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\  argument
801 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\  argument
803 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\  argument
807 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\  argument
809 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\  argument
813 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\  argument
815 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\  argument
834 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\  argument
836 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\  argument
840 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\  argument
842 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\  argument
846 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\  argument
848 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\  argument
852 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\  argument
854 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\  argument
858 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\  argument
860 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\  argument
864 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\  argument
866 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\  argument
870 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\  argument
872 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\  argument
876 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\  argument
878 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\  argument
882 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\  argument
884 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\  argument
888 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\  argument
890 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\  argument
894 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\  argument
896 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\  argument
900 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\  argument
902 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\  argument
906 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\  argument
908 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\  argument
912 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\  argument
914 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\  argument
918 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\  argument
920 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\  argument
924 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\  argument
926 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\  argument
930 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\  argument
932 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\  argument
936 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\  argument
938 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\  argument
947 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\  argument
949 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\  argument
958 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
960 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
964 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
966 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
970 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
972 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
976 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
978 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
987 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
989 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
993 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
995 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
999 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
1001 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
1005 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
1007 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
1017 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\  argument
1019 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\  argument
1028 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\  argument
1030 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\  argument
1039 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\  argument
1041 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\  argument
1045 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\  argument
1047 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\  argument
1057 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\  argument
1059 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\  argument
1068 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\  argument
1070 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\  argument
1079 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\  argument
1081 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\  argument
1085 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\  argument
1087 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\  argument
1092 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\  argument
1094 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\  argument
1103 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\  argument
1105 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\  argument
1114 #define ANA_AC_SDLB_THRES_THRES_SET(x)\  argument
1116 #define ANA_AC_SDLB_THRES_THRES_GET(x)\  argument
1120 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\  argument
1122 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\  argument
1132 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\  argument
1134 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\  argument
1139 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\  argument
1141 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\  argument
1150 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\  argument
1152 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\  argument
1156 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\  argument
1158 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\  argument
1162 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\  argument
1164 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\  argument
1174 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\  argument
1176 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\  argument
1185 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\  argument
1187 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\  argument
1191 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\  argument
1193 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\  argument
1197 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\  argument
1199 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\  argument
1208 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\  argument
1210 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\  argument
1214 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\  argument
1216 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\  argument
1220 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\  argument
1222 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\  argument
1226 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\  argument
1228 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\  argument
1232 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\  argument
1234 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\  argument
1238 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\  argument
1240 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\  argument
1244 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\  argument
1246 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\  argument
1250 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\  argument
1252 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\  argument
1261 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\  argument
1263 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\  argument
1267 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\  argument
1269 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\  argument
1273 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\  argument
1275 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\  argument
1284 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\  argument
1286 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\  argument
1290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\  argument
1292 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\  argument
1296 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\  argument
1298 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\  argument
1302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\  argument
1304 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\  argument
1308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\  argument
1310 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\  argument
1314 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\  argument
1316 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\  argument
1320 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\  argument
1322 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\  argument
1326 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\  argument
1328 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\  argument
1332 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\  argument
1334 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\  argument
1338 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\  argument
1340 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\  argument
1344 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\  argument
1346 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\  argument
1355 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\  argument
1357 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\  argument
1361 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\  argument
1363 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\  argument
1372 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\  argument
1374 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\  argument
1378 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\  argument
1380 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\  argument
1384 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\  argument
1386 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\  argument
1390 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\  argument
1392 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\  argument
1396 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\  argument
1398 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\  argument
1402 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\  argument
1404 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\  argument
1408 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\  argument
1410 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\  argument
1414 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\  argument
1416 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\  argument
1420 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\  argument
1422 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\  argument
1426 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\  argument
1428 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\  argument
1432 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\  argument
1434 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\  argument
1443 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\  argument
1445 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\  argument
1454 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\  argument
1456 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\  argument
1460 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\  argument
1462 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\  argument
1471 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\  argument
1473 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\  argument
1477 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\  argument
1479 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\  argument
1483 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\  argument
1485 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\  argument
1489 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\  argument
1491 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\  argument
1495 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\  argument
1497 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\  argument
1501 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\  argument
1503 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\  argument
1507 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\  argument
1509 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\  argument
1513 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\  argument
1515 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\  argument
1519 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\  argument
1521 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\  argument
1525 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\  argument
1527 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\  argument
1531 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\  argument
1533 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\  argument
1537 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\  argument
1539 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\  argument
1553 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\  argument
1555 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\  argument
1559 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\  argument
1561 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\  argument
1570 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\  argument
1572 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\  argument
1576 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\  argument
1578 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\  argument
1582 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\  argument
1584 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\  argument
1588 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\  argument
1590 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\  argument
1594 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\  argument
1596 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\  argument
1600 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\  argument
1602 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\  argument
1606 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\  argument
1608 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\  argument
1617 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
1619 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
1628 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\  argument
1630 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\  argument
1634 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\  argument
1636 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\  argument
1640 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\  argument
1642 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\  argument
1646 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\  argument
1648 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\  argument
1652 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\  argument
1654 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\  argument
1663 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\  argument
1665 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\  argument
1674 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\  argument
1676 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\  argument
1680 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\  argument
1682 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\  argument
1686 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\  argument
1688 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\  argument
1692 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\  argument
1694 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\  argument
1698 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\  argument
1700 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\  argument
1704 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\  argument
1706 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\  argument
1710 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\  argument
1712 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\  argument
1716 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\  argument
1718 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\  argument
1722 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\  argument
1724 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\  argument
1728 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\  argument
1730 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\  argument
1734 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\  argument
1736 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\  argument
1740 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\  argument
1742 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\  argument
1763 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\  argument
1765 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\  argument
1775 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\  argument
1777 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\  argument
1787 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\  argument
1789 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\  argument
1799 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\  argument
1801 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\  argument
1810 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\  argument
1812 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\  argument
1821 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\  argument
1823 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\  argument
1827 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\  argument
1829 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\  argument
1833 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\  argument
1835 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\  argument
1839 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\  argument
1841 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\  argument
1845 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\  argument
1847 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\  argument
1851 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\  argument
1853 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\  argument
1857 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\  argument
1859 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\  argument
1863 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\  argument
1865 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\  argument
1869 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\  argument
1871 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\  argument
1892 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\  argument
1894 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\  argument
2348 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
2350 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
2359 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2361 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2370 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2372 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2381 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2383 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2392 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2394 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2403 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
2405 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
2414 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2416 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2425 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2427 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2441 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\  argument
2443 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\  argument
2452 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\  argument
2454 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\  argument
2458 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\  argument
2460 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\  argument
2464 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\  argument
2466 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\  argument
2470 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\  argument
2472 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\  argument
2476 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\  argument
2478 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\  argument
2482 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\  argument
2484 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\  argument
2488 #define ASM_PORT_CFG_PAD_ENA_SET(x)\  argument
2490 #define ASM_PORT_CFG_PAD_ENA_GET(x)\  argument
2494 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\  argument
2496 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\  argument
2500 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\  argument
2502 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\  argument
2506 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\  argument
2508 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\  argument
2512 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\  argument
2514 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\  argument
2523 #define ASM_RAM_INIT_RAM_INIT_SET(x)\  argument
2525 #define ASM_RAM_INIT_RAM_INIT_GET(x)\  argument
2529 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2531 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2540 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\  argument
2542 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\  argument
2546 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\  argument
2548 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\  argument
2552 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\  argument
2554 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\  argument
2558 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\  argument
2560 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\  argument
2564 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\  argument
2566 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\  argument
2570 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\  argument
2572 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\  argument
2582 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\  argument
2584 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\  argument
2589 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\  argument
2591 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\  argument
2596 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\  argument
2598 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\  argument
2603 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\  argument
2605 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\  argument
2610 #define CPU_PROC_CTRL_VINITHI_SET(x)\  argument
2612 #define CPU_PROC_CTRL_VINITHI_GET(x)\  argument
2617 #define CPU_PROC_CTRL_CFGTE_SET(x)\  argument
2619 #define CPU_PROC_CTRL_CFGTE_GET(x)\  argument
2624 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\  argument
2626 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\  argument
2631 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\  argument
2633 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\  argument
2638 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\  argument
2640 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\  argument
2645 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\  argument
2647 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\  argument
2652 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\  argument
2654 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\  argument
2659 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\  argument
2661 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\  argument
2666 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\  argument
2668 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\  argument
2678 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\  argument
2680 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\  argument
2685 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\  argument
2687 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\  argument
2697 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\  argument
2699 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\  argument
2704 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\  argument
2706 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\  argument
2715 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
2717 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
2721 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
2723 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
2732 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
2734 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2738 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2740 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2749 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\  argument
2751 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\  argument
2760 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
2762 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
2766 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\  argument
2768 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\  argument
2777 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2779 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2783 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2785 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2789 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2791 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2795 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2797 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2801 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2803 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2807 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
2809 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
2813 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
2815 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
2824 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\  argument
2826 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\  argument
2830 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\  argument
2832 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\  argument
2836 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\  argument
2838 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\  argument
2842 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\  argument
2844 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\  argument
2848 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\  argument
2850 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\  argument
2859 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
2861 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
2865 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2867 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2871 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
2873 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
2877 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
2879 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
2883 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2885 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2889 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2891 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2895 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2897 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2901 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2903 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2907 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2909 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2923 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
2925 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
2934 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
2936 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
2940 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
2942 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
2951 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
2953 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2957 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2959 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2968 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2970 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2974 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2976 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2980 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2982 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2986 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2988 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2992 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2994 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2998 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
3000 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
3004 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
3006 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
3015 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
3017 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
3021 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
3023 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
3027 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
3029 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
3033 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
3035 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
3039 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
3041 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
3045 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
3047 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
3051 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
3053 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
3057 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
3059 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
3063 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
3065 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
3074 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
3076 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
3085 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\  argument
3087 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\  argument
3091 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\  argument
3093 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\  argument
3097 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\  argument
3099 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\  argument
3108 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
3110 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
3114 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
3116 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
3120 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\  argument
3122 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\  argument
3126 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\  argument
3128 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\  argument
3132 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
3134 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
3138 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
3140 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
3144 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
3146 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
3150 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
3152 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
3161 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
3163 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
3167 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
3169 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
3178 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\  argument
3180 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\  argument
3184 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
3186 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
3190 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\  argument
3192 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\  argument
3201 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
3203 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
3212 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
3214 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
3218 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\  argument
3220 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\  argument
3224 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\  argument
3226 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\  argument
3230 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
3232 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
3241 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\  argument
3243 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\  argument
3247 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\  argument
3249 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\  argument
3258 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\  argument
3260 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\  argument
3269 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\  argument
3271 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\  argument
3275 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
3277 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
3281 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
3283 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
3287 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
3289 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
3298 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\  argument
3300 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\  argument
3304 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\  argument
3306 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\  argument
3310 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
3312 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
3316 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\  argument
3318 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\  argument
3322 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\  argument
3324 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\  argument
3333 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\  argument
3335 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\  argument
3339 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3341 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3345 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\  argument
3347 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\  argument
3356 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
3358 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
3362 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
3364 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
3368 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
3370 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
3379 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\  argument
3381 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\  argument
3385 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\  argument
3387 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\  argument
3391 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
3393 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
3402 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
3404 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
3408 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
3410 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
3414 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\  argument
3416 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\  argument
3420 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\  argument
3422 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\  argument
3431 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\  argument
3433 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\  argument
3437 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\  argument
3439 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\  argument
3443 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\  argument
3445 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\  argument
3454 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\  argument
3456 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\  argument
3460 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\  argument
3462 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\  argument
3466 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\  argument
3468 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\  argument
3472 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
3474 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
3483 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\  argument
3485 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\  argument
3489 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\  argument
3491 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\  argument
3495 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
3497 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
3501 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
3503 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
3512 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
3514 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
3518 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\  argument
3520 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\  argument
3529 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\  argument
3531 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\  argument
3535 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\  argument
3537 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\  argument
3541 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\  argument
3543 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\  argument
3547 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\  argument
3549 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\  argument
3553 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\  argument
3555 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\  argument
3559 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\  argument
3561 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\  argument
3565 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\  argument
3567 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\  argument
3571 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\  argument
3573 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\  argument
3577 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\  argument
3579 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\  argument
3583 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
3585 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
3589 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\  argument
3591 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\  argument
3595 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\  argument
3597 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\  argument
3601 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\  argument
3603 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\  argument
3612 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\  argument
3614 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\  argument
3618 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\  argument
3620 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\  argument
3624 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\  argument
3626 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\  argument
3630 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\  argument
3632 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\  argument
3636 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\  argument
3638 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\  argument
3642 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\  argument
3644 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\  argument
3648 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\  argument
3650 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\  argument
3654 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\  argument
3656 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\  argument
3664 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
3666 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
3670 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
3672 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
3680 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
3682 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
3686 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
3688 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
3697 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
3699 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
3703 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
3705 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
3709 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
3711 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
3715 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
3717 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
3721 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
3723 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
3727 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
3729 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
3733 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
3735 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
4139 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
4141 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
4155 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
4157 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
4171 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
4173 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
4187 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
4189 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
4203 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
4205 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
4219 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
4221 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
4235 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
4237 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
4251 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
4253 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
4262 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
4264 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
4268 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
4270 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
4274 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
4276 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
4280 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
4282 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
4286 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
4288 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
4292 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
4294 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
4298 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
4300 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
4304 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
4306 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
4310 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
4312 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
4325 #define DSM_RAM_INIT_RAM_INIT_SET(x)\  argument
4327 #define DSM_RAM_INIT_RAM_INIT_GET(x)\  argument
4331 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4333 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4342 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\  argument
4344 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\  argument
4348 #define DSM_BUF_CFG_AGING_ENA_SET(x)\  argument
4350 #define DSM_BUF_CFG_AGING_ENA_GET(x)\  argument
4354 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\  argument
4356 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\  argument
4360 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\  argument
4362 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\  argument
4371 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\  argument
4373 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\  argument
4377 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\  argument
4379 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\  argument
4383 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\  argument
4385 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\  argument
4389 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\  argument
4391 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\  argument
4400 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\  argument
4402 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\  argument
4406 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\  argument
4408 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\  argument
4417 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\  argument
4419 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\  argument
4423 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\  argument
4425 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\  argument
4429 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\  argument
4431 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\  argument
4435 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\  argument
4437 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\  argument
4446 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\  argument
4448 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\  argument
4457 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\  argument
4459 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\  argument
4468 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\  argument
4470 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\  argument
4474 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\  argument
4476 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\  argument
4480 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\  argument
4482 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\  argument
4486 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\  argument
4488 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\  argument
4492 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\  argument
4494 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\  argument
4499 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\  argument
4501 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\  argument
4506 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\  argument
4508 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\  argument
4513 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\  argument
4515 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\  argument
4524 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\  argument
4526 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\  argument
4530 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\  argument
4532 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\  argument
4536 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\  argument
4538 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\  argument
4542 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\  argument
4544 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\  argument
4558 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\  argument
4560 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\  argument
4564 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\  argument
4566 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\  argument
4570 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\  argument
4572 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\  argument
4576 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\  argument
4578 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\  argument
4582 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\  argument
4584 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\  argument
4588 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\  argument
4590 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\  argument
4599 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\  argument
4601 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\  argument
4605 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\  argument
4607 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\  argument
4611 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\  argument
4613 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\  argument
4617 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\  argument
4619 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\  argument
4623 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\  argument
4625 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\  argument
4629 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\  argument
4631 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\  argument
4635 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\  argument
4637 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\  argument
4641 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\  argument
4643 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\  argument
4652 #define EACL_RAM_INIT_RAM_INIT_SET(x)\  argument
4654 #define EACL_RAM_INIT_RAM_INIT_GET(x)\  argument
4658 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4660 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4669 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
4671 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
4680 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
4682 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
4691 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
4693 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
4723 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\  argument
4725 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\  argument
4730 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
4732 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
4737 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
4739 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
4744 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
4746 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
4750 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
4752 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
4761 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\  argument
4763 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\  argument
4772 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\  argument
4774 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\  argument
4778 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\  argument
4780 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\  argument
4789 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
4791 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
4795 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\  argument
4797 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\  argument
4801 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
4803 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
4807 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\  argument
4809 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\  argument
4813 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\  argument
4815 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\  argument
4824 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\  argument
4826 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\  argument
4835 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\  argument
4837 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\  argument
4846 #define FDMA_INTR_DB_INTR_DB_SET(x)\  argument
4848 #define FDMA_INTR_DB_INTR_DB_GET(x)\  argument
4857 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
4859 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
4868 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\  argument
4870 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\  argument
4874 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\  argument
4876 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\  argument
4885 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\  argument
4887 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\  argument
4891 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\  argument
4893 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\  argument
4897 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\  argument
4899 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\  argument
4903 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\  argument
4905 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\  argument
4909 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\  argument
4911 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\  argument
4915 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\  argument
4917 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\  argument
4921 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\  argument
4923 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\  argument
4927 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\  argument
4929 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\  argument
4938 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\  argument
4940 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\  argument
4949 #define FDMA_CTRL_NRESET_SET(x)\  argument
4951 #define FDMA_CTRL_NRESET_GET(x)\  argument
4960 #define GCB_CHIP_ID_REV_ID_SET(x)\  argument
4962 #define GCB_CHIP_ID_REV_ID_GET(x)\  argument
4966 #define GCB_CHIP_ID_PART_ID_SET(x)\  argument
4968 #define GCB_CHIP_ID_PART_ID_GET(x)\  argument
4972 #define GCB_CHIP_ID_MFG_ID_SET(x)\  argument
4974 #define GCB_CHIP_ID_MFG_ID_GET(x)\  argument
4978 #define GCB_CHIP_ID_ONE_SET(x)\  argument
4980 #define GCB_CHIP_ID_ONE_GET(x)\  argument
4990 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\  argument
4992 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\  argument
4996 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\  argument
4998 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\  argument
5002 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\  argument
5004 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\  argument
5014 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\  argument
5016 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\  argument
5020 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\  argument
5022 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\  argument
5033 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\  argument
5035 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\  argument
5044 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\  argument
5046 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\  argument
5050 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\  argument
5052 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\  argument
5061 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\  argument
5063 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\  argument
5067 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\  argument
5069 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\  argument
5078 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\  argument
5080 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\  argument
5084 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\  argument
5086 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\  argument
5096 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\  argument
5098 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\  argument
5102 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\  argument
5104 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\  argument
5108 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\  argument
5110 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\  argument
5114 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\  argument
5116 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\  argument
5120 #define HSCH_SE_CFG_SE_STOP_SET(x)\  argument
5122 #define HSCH_SE_CFG_SE_STOP_GET(x)\  argument
5132 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\  argument
5134 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\  argument
5143 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\  argument
5145 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\  argument
5150 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\  argument
5152 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\  argument
5156 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\  argument
5158 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\  argument
5162 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\  argument
5164 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\  argument
5168 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\  argument
5170 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\  argument
5179 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\  argument
5181 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\  argument
5185 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\  argument
5187 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\  argument
5197 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\  argument
5199 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\  argument
5203 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\  argument
5205 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\  argument
5209 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\  argument
5211 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\  argument
5221 #define HSCH_SYS_CLK_PER_100PS_SET(x)\  argument
5223 #define HSCH_SYS_CLK_PER_100PS_GET(x)\  argument
5232 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\  argument
5234 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\  argument
5244 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\  argument
5246 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\  argument
5250 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\  argument
5252 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\  argument
5261 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\  argument
5263 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\  argument
5267 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\  argument
5269 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\  argument
5273 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\  argument
5275 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\  argument
5280 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\  argument
5282 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\  argument
5286 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\  argument
5288 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\  argument
5292 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\  argument
5294 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\  argument
5299 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\  argument
5301 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\  argument
5310 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
5312 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
5316 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\  argument
5318 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\  argument
5322 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\  argument
5324 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\  argument
5328 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\  argument
5330 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\  argument
5334 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\  argument
5336 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\  argument
5345 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\  argument
5347 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\  argument
5356 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\  argument
5358 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\  argument
5367 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\  argument
5369 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\  argument
5378 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\  argument
5380 #define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\  argument
5389 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\  argument
5391 #define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\  argument
5395 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\  argument
5397 #define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\  argument
5401 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\  argument
5403 #define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\  argument
5412 #define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\  argument
5414 #define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\  argument
5418 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\  argument
5420 #define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\  argument
5424 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\  argument
5426 #define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\  argument
5430 #define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\  argument
5432 #define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\  argument
5440 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\  argument
5442 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\  argument
5446 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\  argument
5448 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\  argument
5453 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\  argument
5455 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\  argument
5459 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\  argument
5461 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\  argument
5465 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\  argument
5467 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\  argument
5475 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\  argument
5477 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\  argument
5481 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\  argument
5483 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\  argument
5495 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\  argument
5497 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\  argument
5501 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\  argument
5503 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\  argument
5507 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\  argument
5509 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\  argument
5513 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\  argument
5515 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\  argument
5519 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\  argument
5521 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\  argument
5525 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\  argument
5527 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\  argument
5531 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\  argument
5533 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\  argument
5537 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\  argument
5539 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\  argument
5543 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\  argument
5545 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\  argument
5549 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\  argument
5551 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\  argument
5555 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\  argument
5557 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\  argument
5561 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\  argument
5563 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\  argument
5572 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\  argument
5574 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\  argument
5582 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\  argument
5584 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\  argument
5588 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\  argument
5590 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\  argument
5594 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\  argument
5596 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\  argument
5600 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\  argument
5602 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\  argument
5606 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\  argument
5608 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\  argument
5612 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\  argument
5614 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\  argument
5618 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\  argument
5620 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\  argument
5624 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\  argument
5626 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\  argument
5630 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\  argument
5632 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\  argument
5636 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\  argument
5638 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\  argument
5642 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\  argument
5644 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\  argument
5648 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\  argument
5650 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\  argument
5654 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\  argument
5656 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\  argument
5660 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\  argument
5662 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\  argument
5666 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\  argument
5668 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\  argument
5676 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\  argument
5678 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\  argument
5682 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\  argument
5684 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\  argument
5692 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\  argument
5694 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\  argument
5698 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\  argument
5700 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\  argument
5708 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\  argument
5710 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\  argument
5714 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\  argument
5716 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\  argument
5720 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\  argument
5722 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\  argument
5726 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\  argument
5728 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\  argument
5732 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\  argument
5734 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\  argument
5738 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\  argument
5740 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\  argument
5744 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\  argument
5746 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\  argument
5755 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\  argument
5757 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\  argument
5761 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\  argument
5763 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\  argument
5772 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\  argument
5774 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\  argument
5778 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\  argument
5780 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\  argument
5784 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\  argument
5786 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\  argument
5790 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\  argument
5792 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\  argument
5796 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\  argument
5798 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\  argument
5802 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\  argument
5804 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\  argument
5808 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\  argument
5810 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\  argument
5814 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\  argument
5816 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\  argument
5820 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\  argument
5822 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\  argument
5826 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\  argument
5828 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\  argument
5837 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\  argument
5839 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\  argument
5843 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\  argument
5845 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\  argument
5859 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\  argument
5861 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\  argument
5865 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\  argument
5867 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\  argument
5886 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\  argument
5888 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\  argument
5892 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\  argument
5894 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\  argument
5903 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
5905 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
5909 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
5911 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
5915 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
5917 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
5921 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
5923 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
5927 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
5929 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
5933 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
5935 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
5939 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
5941 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
5945 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
5947 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
5951 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
5953 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
5957 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
5959 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
5963 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
5965 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
5969 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
5971 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
5980 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
5982 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
5986 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
5988 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
5992 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
5994 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
6003 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
6005 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
6009 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
6011 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
6015 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
6017 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
6021 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
6023 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
6027 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
6029 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
6033 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
6035 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
6039 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
6041 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
6045 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
6047 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
6051 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
6053 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
6057 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
6059 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
6063 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
6065 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
6069 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
6071 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
6080 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
6082 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
6086 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
6088 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
6092 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
6094 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
6103 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
6105 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
6109 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
6111 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
6115 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
6117 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
6121 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
6123 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
6127 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
6129 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
6133 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
6135 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
6139 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
6141 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
6145 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
6147 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
6151 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
6153 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
6157 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
6159 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
6163 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
6165 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
6169 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
6171 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
6180 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
6182 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
6186 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
6188 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
6192 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
6194 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
6203 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\  argument
6205 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\  argument
6210 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\  argument
6212 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\  argument
6217 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\  argument
6219 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\  argument
6224 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\  argument
6226 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\  argument
6231 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\  argument
6233 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\  argument
6238 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\  argument
6240 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\  argument
6245 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\  argument
6247 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\  argument
6252 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\  argument
6254 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\  argument
6259 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\  argument
6261 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\  argument
6265 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\  argument
6267 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\  argument
6272 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\  argument
6274 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\  argument
6279 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\  argument
6281 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\  argument
6286 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\  argument
6288 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\  argument
6296 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\  argument
6298 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\  argument
6303 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\  argument
6305 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\  argument
6310 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\  argument
6312 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\  argument
6317 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\  argument
6319 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\  argument
6324 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\  argument
6326 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\  argument
6331 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\  argument
6333 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\  argument
6338 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\  argument
6340 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\  argument
6345 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\  argument
6347 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\  argument
6352 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\  argument
6354 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\  argument
6359 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\  argument
6361 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\  argument
6366 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\  argument
6368 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\  argument
6373 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\  argument
6375 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\  argument
6384 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\  argument
6386 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\  argument
6390 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\  argument
6392 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\  argument
6396 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\  argument
6398 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\  argument
6402 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\  argument
6404 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\  argument
6408 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\  argument
6410 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\  argument
6414 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\  argument
6416 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\  argument
6420 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\  argument
6422 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\  argument
6426 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\  argument
6428 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\  argument
6436 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\  argument
6438 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\  argument
6442 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\  argument
6444 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\  argument
6448 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\  argument
6450 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\  argument
6454 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\  argument
6456 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\  argument
6460 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\  argument
6462 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\  argument
6466 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\  argument
6468 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\  argument
6473 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\  argument
6475 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\  argument
6480 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\  argument
6482 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\  argument
6487 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\  argument
6489 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\  argument
6494 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\  argument
6496 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\  argument
6501 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\  argument
6503 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\  argument
6508 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\  argument
6510 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\  argument
6519 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\  argument
6521 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\  argument
6525 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\  argument
6527 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\  argument
6531 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\  argument
6533 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\  argument
6537 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\  argument
6539 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\  argument
6543 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\  argument
6545 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\  argument
6549 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\  argument
6551 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\  argument
6555 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\  argument
6557 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\  argument
6567 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\  argument
6569 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\  argument
6579 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\  argument
6581 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\  argument
6591 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\  argument
6593 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\  argument
6602 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\  argument
6604 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\  argument
6608 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\  argument
6610 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\  argument
6614 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\  argument
6616 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\  argument
6620 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\  argument
6622 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\  argument
6636 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\  argument
6638 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\  argument
6647 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\  argument
6649 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\  argument
6663 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\  argument
6665 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\  argument
6680 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\  argument
6682 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\  argument
6687 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\  argument
6689 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\  argument
6694 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\  argument
6696 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\  argument
6701 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\  argument
6703 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\  argument
6707 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\  argument
6709 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\  argument
6713 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\  argument
6715 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\  argument
6719 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\  argument
6721 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\  argument
6725 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\  argument
6727 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\  argument
6731 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\  argument
6733 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\  argument
6742 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\  argument
6744 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\  argument
6758 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\  argument
6760 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\  argument
6769 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\  argument
6771 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\  argument
6785 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\  argument
6787 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\  argument
6796 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\  argument
6798 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\  argument
6807 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\  argument
6809 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\  argument
6813 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\  argument
6815 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\  argument
6826 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\  argument
6828 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\  argument
6833 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\  argument
6835 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\  argument
6840 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\  argument
6842 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\  argument
6846 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\  argument
6848 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\  argument
6863 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\  argument
6865 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\  argument
6869 #define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\  argument
6871 #define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\  argument
6875 #define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\  argument
6877 #define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\  argument
6881 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
6883 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
6887 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
6889 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
6893 #define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\  argument
6895 #define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\  argument
6904 #define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\  argument
6906 #define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\  argument
6915 #define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\  argument
6917 #define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\  argument
6926 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\  argument
6928 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\  argument
6932 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\  argument
6934 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\  argument
6938 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\  argument
6940 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\  argument
6944 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
6946 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
6950 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\  argument
6952 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\  argument
6956 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\  argument
6958 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\  argument
6962 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\  argument
6964 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\  argument
6968 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\  argument
6970 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\  argument
6974 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\  argument
6976 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\  argument
6985 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\  argument
6987 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\  argument
6996 #define QRES_RES_CFG_WM_HIGH_SET(x)\  argument
6998 #define QRES_RES_CFG_WM_HIGH_GET(x)\  argument
7007 #define QRES_RES_STAT_MAXUSE_SET(x)\  argument
7009 #define QRES_RES_STAT_MAXUSE_GET(x)\  argument
7018 #define QRES_RES_STAT_CUR_INUSE_SET(x)\  argument
7020 #define QRES_RES_STAT_CUR_INUSE_GET(x)\  argument
7028 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
7030 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
7034 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\  argument
7036 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\  argument
7040 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
7042 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
7054 #define QS_XTR_FLUSH_FLUSH_SET(x)\  argument
7056 #define QS_XTR_FLUSH_FLUSH_GET(x)\  argument
7064 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\  argument
7066 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\  argument
7074 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
7076 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
7080 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
7082 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
7094 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
7096 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
7100 #define QS_INJ_CTRL_ABORT_SET(x)\  argument
7102 #define QS_INJ_CTRL_ABORT_GET(x)\  argument
7106 #define QS_INJ_CTRL_EOF_SET(x)\  argument
7108 #define QS_INJ_CTRL_EOF_GET(x)\  argument
7112 #define QS_INJ_CTRL_SOF_SET(x)\  argument
7114 #define QS_INJ_CTRL_SOF_GET(x)\  argument
7118 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
7120 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
7128 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
7130 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
7134 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
7136 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
7140 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\  argument
7142 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\  argument
7152 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
7154 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
7159 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
7161 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
7165 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
7167 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
7171 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\  argument
7173 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\  argument
7183 #define QSYS_ATOP_ATOP_SET(x)\  argument
7185 #define QSYS_ATOP_ATOP_GET(x)\  argument
7194 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\  argument
7196 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\  argument
7200 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\  argument
7202 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\  argument
7212 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\  argument
7214 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\  argument
7223 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\  argument
7225 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\  argument
7234 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\  argument
7236 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\  argument
7240 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\  argument
7242 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\  argument
7246 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\  argument
7248 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\  argument
7257 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\  argument
7259 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\  argument
7263 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
7265 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
7274 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\  argument
7276 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\  argument
7286 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\  argument
7288 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\  argument
7292 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\  argument
7294 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\  argument
7298 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\  argument
7300 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\  argument
7309 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\  argument
7311 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\  argument
7315 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\  argument
7317 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\  argument
7321 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\  argument
7323 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\  argument
7327 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\  argument
7329 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\  argument
7333 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\  argument
7335 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\  argument
7339 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\  argument
7341 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\  argument
7350 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\  argument
7352 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\  argument
7356 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\  argument
7358 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\  argument
7362 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
7364 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
7373 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\  argument
7375 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\  argument
7384 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\  argument
7386 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\  argument
7395 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\  argument
7397 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\  argument
7406 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\  argument
7408 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\  argument
7417 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\  argument
7419 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\  argument
7423 #define REW_TAG_CTRL_TAG_CFG_SET(x)\  argument
7425 #define REW_TAG_CTRL_TAG_CFG_GET(x)\  argument
7429 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\  argument
7431 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\  argument
7435 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\  argument
7437 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\  argument
7441 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\  argument
7443 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\  argument
7447 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\  argument
7449 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\  argument
7458 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\  argument
7460 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\  argument
7464 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\  argument
7466 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\  argument
7475 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\  argument
7477 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\  argument
7481 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\  argument
7483 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\  argument
7487 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\  argument
7489 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\  argument
7493 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
7495 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
7499 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
7501 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
7505 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\  argument
7507 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\  argument
7516 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\  argument
7518 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\  argument
7527 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\  argument
7529 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\  argument
7548 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\  argument
7550 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\  argument
7559 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\  argument
7561 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\  argument
7565 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\  argument
7567 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\  argument
7576 #define REW_RAM_INIT_RAM_INIT_SET(x)\  argument
7578 #define REW_RAM_INIT_RAM_INIT_GET(x)\  argument
7582 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
7584 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
7592 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\  argument
7594 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\  argument
7598 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\  argument
7600 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\  argument
7604 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\  argument
7606 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\  argument
7610 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\  argument
7612 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\  argument
7616 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\  argument
7618 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\  argument
7622 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\  argument
7624 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\  argument
7628 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\  argument
7630 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\  argument
7634 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\  argument
7636 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\  argument
7644 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\  argument
7646 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\  argument
7650 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\  argument
7652 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\  argument
7684 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\  argument
7686 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\  argument
7694 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\  argument
7696 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\  argument
7704 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\  argument
7706 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\  argument
7754 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\  argument
7756 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\  argument
7760 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\  argument
7762 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\  argument
7766 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\  argument
7768 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\  argument
7772 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\  argument
7774 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\  argument
7778 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\  argument
7780 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\  argument
7784 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\  argument
7786 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\  argument
7790 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\  argument
7792 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\  argument
7796 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\  argument
7798 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\  argument
7806 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\  argument
7808 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\  argument
7812 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\  argument
7814 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\  argument
7846 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\  argument
7848 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\  argument
7856 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\  argument
7858 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\  argument
7866 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\  argument
7868 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\  argument
7916 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\  argument
7918 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\  argument
7922 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\  argument
7924 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\  argument
7928 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\  argument
7930 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\  argument
7934 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\  argument
7936 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\  argument
7940 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\  argument
7942 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\  argument
7946 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\  argument
7948 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\  argument
7952 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\  argument
7954 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\  argument
7958 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\  argument
7960 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\  argument
7968 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\  argument
7970 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\  argument
7974 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\  argument
7976 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\  argument
8008 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\  argument
8010 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\  argument
8018 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\  argument
8020 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\  argument
8068 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\  argument
8070 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\  argument
8074 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
8076 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
8085 #define VOP_RAM_INIT_RAM_INIT_SET(x)\  argument
8087 #define VOP_RAM_INIT_RAM_INIT_GET(x)\  argument
8091 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
8093 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
8102 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\  argument
8104 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\  argument
8109 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\  argument
8111 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\  argument
8115 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\  argument
8117 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\  argument
8121 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\  argument
8123 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\  argument
8133 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\  argument
8135 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\  argument
8145 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\  argument
8147 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\  argument
8157 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\  argument
8159 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\  argument
8169 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\  argument
8171 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\  argument
8184 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
8186 #define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
8195 #define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
8197 #define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
8201 #define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
8203 #define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
8212 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
8214 #define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
8218 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\  argument
8220 #define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\  argument
8224 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\  argument
8226 #define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\  argument
8230 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
8232 #define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
8241 #define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
8243 #define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
8247 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
8249 #define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
8253 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
8255 #define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument