Lines Matching +full:2 +full:rgmii
11 #define LAN969X_RGMII_TX_CLK_SEL_25MHZ 2 /* 100Mbps */
17 #define LAN969X_RGMII_SPEED_SEL_1000 2 /* Select 1000Mbps speed */
20 #define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2 /* Phase shift 45deg */
27 #define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */
78 dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); in lan969x_rgmii_get_clk_delay_sel()
85 /* Configure the RGMII tx clock frequency. */
92 /* Take the RGMII clock domain out of reset and set tx clock in lan969x_rgmii_tx_clk_config()
104 /* Configure the RGMII port device. */
144 /* Configure the RGMII delay lines in the MAC.
200 /* Configure GPIO's to be used as RGMII interface. */
205 /* Enable the RGMII on the GPIOs. */ in lan969x_rgmii_gpio_config()