Lines Matching +full:tx +full:- +full:port +full:- +full:mapping

1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
8  * Tx header version.
11 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
15  * 0 - Ethernet control (e.g. EMADs, LACP)
16  * 1 - Ethernet data
18 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
23 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
28 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
34 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
39 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
45 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
48  * Destination local port for unicast packets.
51  * Control packets are directed to a specific egress port, while data
52  * packets are transmitted through the CPU port (0) into the switch partition,
55 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
59  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
62 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16);
65  * 0 - Data packets
66  * 6 - Control packets
68 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);