Lines Matching +full:in +full:- +full:between

1 # SPDX-License-Identifier: GPL-2.0-only
5 	  Mailbox is a framework to control hardware communication between
6 	  on-chip processors through queued messages and interrupt driven
17 	  used in Secure mode only.
24 	  which provides unidirectional mailboxes between processing elements.
33 	  which provides unidirectional mailboxes between processing elements.
37 	  will be discovered and possibly managed at probe-time.
64 	  which can be used in Secure mode only.
72 	  send short messages between Highbank's A9 cores and the EnergyCore
82 	  running on the Cortex-M3 rWTM secure processor of the Armada 37xx
91 	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
92 	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
99 	  This driver provides support for inter-processor communication
100 	  between CPU cores and MCU processor on Some Rockchip SOCs.
110 	  between the OS and a platform such as the BMC. This medium
121 	  to send message between processors. Say Y here if you want to use the
147 	  and K3 architecture SoCs. These may be used for communication between
158 	  between application processors and other processors/MCU/DSP. Select
168 	  between application processors and MCU. Say Y here if you want to
188 	  module will be called mailbox-mpfs.
193 	tristate "Microchip Inter-processor Communication (IPC) SBI driver"
198 	  Inter-process communication (IPC) controller.
201 	  module will be called mailbox-mchp-ipc-sbi.
210 	  providing an interface for invoking the inter-process communication
218 	  between different remote processors and host processors on Tegra186
223 	tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
226 	  An implementation of the APM X-Gene Interprocessor Communication
227 	  Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
228 	  It is used to send short messages between ARM64-bit cores and
230 	  want to use the APM X-Gene SLIMpro IPCM support.
256 	  with hardware for Inter-Processor Communication Controller (IPCC)
257 	  between processors. Say Y here if you want to have this support.
265           between processors with ADSP. It will place the message to share
284 	  between processors with Xilinx ZynqMP IPI. It will place the
293 	  Mailbox implementation for the hardware message box present in
295 	  between the application CPUs and the power management coprocessor.
302 	  to send message between application processors and MCU. Say Y here if
310 	  controller driver enables communication between AP and CPUCP. Say
317 	  Qualcomm Technologies, Inc. Inter-Processor Communication Controller
324 	tristate "T-head TH1520 Mailbox"
327 	  Mailbox driver implementation for the Thead TH-1520 platform. Enables
329 	  messages. Could be used to communicate between E910 core, on which the