Lines Matching +full:meson +full:- +full:axg +full:- +full:hhi +full:- +full:sysctrl
1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
96 (8 + (((_chan) - 2) * 3))
153 * and u-boot source served as reference). These only seem to be relevant on
378 for (i = 0; i < indio_dev->num_channels; i++) in find_channel_by_num()
379 if (indio_dev->channels[i].channel == num) in find_channel_by_num()
380 return &indio_dev->channels[i]; in find_channel_by_num()
389 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_get_fifo_count()
400 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; in meson_sar_adc_calib_val()
402 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); in meson_sar_adc_calib_val()
416 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val, in meson_sar_adc_wait_busy_clear()
428 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_set_chan7_mux()
433 priv->chan7_mux_sel = sel; in meson_sar_adc_set_chan7_mux()
441 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_read_raw_sample()
444 if (!wait_for_completion_timeout(&priv->done, in meson_sar_adc_read_raw_sample()
446 return -ETIMEDOUT; in meson_sar_adc_read_raw_sample()
451 return -EINVAL; in meson_sar_adc_read_raw_sample()
454 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); in meson_sar_adc_read_raw_sample()
456 if (fifo_chan != chan->address) { in meson_sar_adc_read_raw_sample()
458 fifo_chan, chan->address); in meson_sar_adc_read_raw_sample()
459 return -EINVAL; in meson_sar_adc_read_raw_sample()
463 fifo_val &= GENMASK(priv->param->resolution - 1, 0); in meson_sar_adc_read_raw_sample()
475 int val, address = chan->address; in meson_sar_adc_set_averaging()
478 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
483 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
499 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
504 chan->address); in meson_sar_adc_enable_channel()
505 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
509 chan->address); in meson_sar_adc_enable_channel()
510 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
515 chan->address); in meson_sar_adc_enable_channel()
516 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
520 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { in meson_sar_adc_enable_channel()
521 if (chan->type == IIO_TEMP) in meson_sar_adc_enable_channel()
526 regmap_update_bits(priv->regmap, in meson_sar_adc_enable_channel()
529 } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) { in meson_sar_adc_enable_channel()
532 if (chan->channel == NUM_CHAN_7) in meson_sar_adc_enable_channel()
535 sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS]; in meson_sar_adc_enable_channel()
536 if (sel != priv->chan7_mux_sel) in meson_sar_adc_enable_channel()
545 reinit_completion(&priv->done); in meson_sar_adc_start_sample_engine()
547 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
550 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
553 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
561 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
564 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
570 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
579 mutex_lock(&priv->lock); in meson_sar_adc_lock()
581 if (priv->param->has_bl30_integration) { in meson_sar_adc_lock()
583 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_lock()
592 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val, in meson_sar_adc_lock()
596 mutex_unlock(&priv->lock); in meson_sar_adc_lock()
608 if (priv->param->has_bl30_integration) in meson_sar_adc_unlock()
610 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_unlock()
613 mutex_unlock(&priv->lock); in meson_sar_adc_unlock()
625 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); in meson_sar_adc_clear_fifo()
636 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_get_sample()
639 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) in meson_sar_adc_get_sample()
640 return -ENOTSUPP; in meson_sar_adc_get_sample()
661 chan->address, ret); in meson_sar_adc_get_sample()
673 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_iio_info_read_raw()
687 if (chan->type == IIO_VOLTAGE) { in meson_sar_adc_iio_info_read_raw()
688 ret = regulator_get_voltage(priv->vref); in meson_sar_adc_iio_info_read_raw()
695 *val2 = priv->param->resolution; in meson_sar_adc_iio_info_read_raw()
697 } else if (chan->type == IIO_TEMP) { in meson_sar_adc_iio_info_read_raw()
699 *val = priv->param->temperature_multiplier; in meson_sar_adc_iio_info_read_raw()
700 *val2 = priv->param->temperature_divider; in meson_sar_adc_iio_info_read_raw()
707 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
711 *val = priv->calibbias; in meson_sar_adc_iio_info_read_raw()
715 *val = priv->calibscale / MILLION; in meson_sar_adc_iio_info_read_raw()
716 *val2 = priv->calibscale % MILLION; in meson_sar_adc_iio_info_read_raw()
721 priv->param->temperature_divider, in meson_sar_adc_iio_info_read_raw()
722 priv->param->temperature_multiplier); in meson_sar_adc_iio_info_read_raw()
723 *val -= priv->temperature_sensor_adc_val; in meson_sar_adc_iio_info_read_raw()
727 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
735 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_clk_init()
741 return -ENOMEM; in meson_sar_adc_clk_init()
745 clk_parents[0] = __clk_get_name(priv->clkin); in meson_sar_adc_clk_init()
749 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
750 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; in meson_sar_adc_clk_init()
751 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; in meson_sar_adc_clk_init()
752 priv->clk_div.hw.init = &init; in meson_sar_adc_clk_init()
753 priv->clk_div.flags = 0; in meson_sar_adc_clk_init()
755 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw); in meson_sar_adc_clk_init()
756 if (WARN_ON(IS_ERR(priv->adc_div_clk))) in meson_sar_adc_clk_init()
757 return PTR_ERR(priv->adc_div_clk); in meson_sar_adc_clk_init()
761 return -ENOMEM; in meson_sar_adc_clk_init()
765 clk_parents[0] = __clk_get_name(priv->adc_div_clk); in meson_sar_adc_clk_init()
769 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
770 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); in meson_sar_adc_clk_init()
771 priv->clk_gate.hw.init = &init; in meson_sar_adc_clk_init()
773 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); in meson_sar_adc_clk_init()
774 if (WARN_ON(IS_ERR(priv->adc_clk))) in meson_sar_adc_clk_init()
775 return PTR_ERR(priv->adc_clk); in meson_sar_adc_clk_init()
784 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_temp_sensor_init()
795 * was passed via nvmem-cells. in meson_sar_adc_temp_sensor_init()
797 if (ret == -ENODEV) in meson_sar_adc_temp_sensor_init()
803 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); in meson_sar_adc_temp_sensor_init()
804 if (IS_ERR(priv->tsc_regmap)) in meson_sar_adc_temp_sensor_init()
805 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), in meson_sar_adc_temp_sensor_init()
806 "failed to get amlogic,hhi-sysctrl regmap\n"); in meson_sar_adc_temp_sensor_init()
814 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); in meson_sar_adc_temp_sensor_init()
817 trimming_bits = priv->param->temperature_trimming_bits; in meson_sar_adc_temp_sensor_init()
818 trimming_mask = BIT(trimming_bits) - 1; in meson_sar_adc_temp_sensor_init()
820 priv->temperature_sensor_calibrated = in meson_sar_adc_temp_sensor_init()
822 priv->temperature_sensor_coefficient = buf[2] & trimming_mask; in meson_sar_adc_temp_sensor_init()
827 priv->temperature_sensor_adc_val = buf[2]; in meson_sar_adc_temp_sensor_init()
828 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; in meson_sar_adc_temp_sensor_init()
829 priv->temperature_sensor_adc_val >>= trimming_bits; in meson_sar_adc_temp_sensor_init()
839 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_init()
848 if (priv->param->has_bl30_integration) { in meson_sar_adc_init()
854 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); in meson_sar_adc_init()
865 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_init()
869 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); in meson_sar_adc_init()
871 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
873 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
877 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
881 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
887 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
891 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
901 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
905 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
909 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
912 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
915 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
918 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
932 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); in meson_sar_adc_init()
934 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_init()
935 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
937 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
945 priv->temperature_sensor_coefficient); in meson_sar_adc_init()
946 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
949 if (priv->param->temperature_trimming_bits == 5) { in meson_sar_adc_init()
950 if (priv->temperature_sensor_coefficient & BIT(4)) in meson_sar_adc_init()
957 * of the TSC is located in the HHI register area. in meson_sar_adc_init()
959 regmap_update_bits(priv->tsc_regmap, in meson_sar_adc_init()
965 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
967 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
972 priv->param->disable_ring_counter); in meson_sar_adc_init()
973 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
977 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) { in meson_sar_adc_init()
978 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc); in meson_sar_adc_init()
979 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
982 if (priv->param->has_vref_select) { in meson_sar_adc_init()
984 priv->param->vref_select); in meson_sar_adc_init()
985 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
990 priv->param->vref_voltage); in meson_sar_adc_init()
991 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
995 priv->param->cmv_select); in meson_sar_adc_init()
996 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_init()
1000 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); in meson_sar_adc_init()
1004 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); in meson_sar_adc_init()
1015 if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) in meson_sar_adc_set_bandgap()
1016 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, in meson_sar_adc_set_bandgap()
1020 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_set_bandgap()
1028 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_hw_enable()
1038 ret = regulator_enable(priv->vref); in meson_sar_adc_hw_enable()
1045 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_hw_enable()
1050 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
1055 ret = clk_prepare_enable(priv->adc_clk); in meson_sar_adc_hw_enable()
1066 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
1069 regulator_disable(priv->vref); in meson_sar_adc_hw_enable()
1087 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret)); in meson_sar_adc_hw_disable()
1089 clk_disable_unprepare(priv->adc_clk); in meson_sar_adc_hw_disable()
1091 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_disable()
1096 regulator_disable(priv->vref); in meson_sar_adc_hw_disable()
1109 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_irq()
1116 complete(&priv->done); in meson_sar_adc_irq()
1127 nominal0 = (1 << priv->param->resolution) / 4; in meson_sar_adc_calib()
1128 nominal1 = (1 << priv->param->resolution) * 3 / 4; in meson_sar_adc_calib()
1149 ret = -EINVAL; in meson_sar_adc_calib()
1153 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, in meson_sar_adc_calib()
1154 value1 - value0); in meson_sar_adc_calib()
1155 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, in meson_sar_adc_calib()
1168 if (chan->type == IIO_TEMP) in read_label()
1169 return sprintf(label, "temp-sensor\n"); in read_label()
1170 if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS) in read_label()
1172 chan7_mux_names[chan->channel - NUM_MUX_0_VSS]); in read_label()
1173 if (chan->type == IIO_VOLTAGE) in read_label()
1174 return sprintf(label, "channel-%d\n", chan->channel); in read_label()
1247 .name = "meson-meson8-saradc",
1252 .name = "meson-meson8b-saradc",
1257 .name = "meson-meson8m2-saradc",
1262 .name = "meson-gxbb-saradc",
1267 .name = "meson-gxl-saradc",
1272 .name = "meson-gxm-saradc",
1277 .name = "meson-axg-saradc",
1282 .name = "meson-g12a-saradc",
1287 .compatible = "amlogic,meson8-saradc",
1290 .compatible = "amlogic,meson8b-saradc",
1293 .compatible = "amlogic,meson8m2-saradc",
1296 .compatible = "amlogic,meson-gxbb-saradc",
1299 .compatible = "amlogic,meson-gxl-saradc",
1302 .compatible = "amlogic,meson-gxm-saradc",
1305 .compatible = "amlogic,meson-axg-saradc",
1308 .compatible = "amlogic,meson-g12a-saradc",
1319 struct device *dev = &pdev->dev; in meson_sar_adc_probe()
1326 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n"); in meson_sar_adc_probe()
1329 init_completion(&priv->done); in meson_sar_adc_probe()
1333 return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); in meson_sar_adc_probe()
1335 priv->param = match_data->param; in meson_sar_adc_probe()
1337 indio_dev->name = match_data->name; in meson_sar_adc_probe()
1338 indio_dev->modes = INDIO_DIRECT_MODE; in meson_sar_adc_probe()
1339 indio_dev->info = &meson_sar_adc_iio_info; in meson_sar_adc_probe()
1345 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); in meson_sar_adc_probe()
1346 if (IS_ERR(priv->regmap)) in meson_sar_adc_probe()
1347 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n"); in meson_sar_adc_probe()
1349 irq = irq_of_parse_and_map(dev->of_node, 0); in meson_sar_adc_probe()
1351 return dev_err_probe(dev, -EINVAL, "failed to get irq\n"); in meson_sar_adc_probe()
1357 priv->clkin = devm_clk_get(dev, "clkin"); in meson_sar_adc_probe()
1358 if (IS_ERR(priv->clkin)) in meson_sar_adc_probe()
1359 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); in meson_sar_adc_probe()
1361 priv->core_clk = devm_clk_get_enabled(dev, "core"); in meson_sar_adc_probe()
1362 if (IS_ERR(priv->core_clk)) in meson_sar_adc_probe()
1363 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); in meson_sar_adc_probe()
1365 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); in meson_sar_adc_probe()
1366 if (IS_ERR(priv->adc_clk)) in meson_sar_adc_probe()
1367 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); in meson_sar_adc_probe()
1369 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); in meson_sar_adc_probe()
1370 if (IS_ERR(priv->adc_sel_clk)) in meson_sar_adc_probe()
1371 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); in meson_sar_adc_probe()
1373 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ in meson_sar_adc_probe()
1374 if (!priv->adc_clk) { in meson_sar_adc_probe()
1380 priv->vref = devm_regulator_get(dev, "vref"); in meson_sar_adc_probe()
1381 if (IS_ERR(priv->vref)) in meson_sar_adc_probe()
1382 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n"); in meson_sar_adc_probe()
1384 priv->calibscale = MILLION; in meson_sar_adc_probe()
1386 if (priv->param->temperature_trimming_bits) { in meson_sar_adc_probe()
1392 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_probe()
1393 indio_dev->channels = meson_sar_adc_and_temp_iio_channels; in meson_sar_adc_probe()
1394 indio_dev->num_channels = in meson_sar_adc_probe()
1397 indio_dev->channels = meson_sar_adc_iio_channels; in meson_sar_adc_probe()
1398 indio_dev->num_channels = in meson_sar_adc_probe()
1406 mutex_init(&priv->lock); in meson_sar_adc_probe()
1448 clk_disable_unprepare(priv->core_clk); in meson_sar_adc_suspend()
1459 ret = clk_prepare_enable(priv->core_clk); in meson_sar_adc_resume()
1475 .name = "meson-saradc",
1484 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");