Lines Matching +full:memory +full:- +full:controllers
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define SKX_NUM_IMC 2 /* Memory controllers per socket */
33 #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
60 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
61 * memory errors should fit one of these masks:
72 * Errors from either the memory of the 1-level memory system or the
73 * 2nd level memory (the slow "far" memory) of the 2-level memory system.
77 * Errors from the 1st level memory (the fast "near" memory as cache)
78 * of the 2-level memory system.
85 * memory controllers on the die.
94 struct pci_dev *pcu_cr3; /* for HBM memory detection */
97 * Some server BIOS may hide certain memory controllers, and the
98 * EDAC driver skips those hidden memory controllers. However, the
99 * ADXL still decodes memory error address using physical memory
102 * (used the EDAC driver) of present memory controllers during the
111 int num_channels; /* channels per memory controller */
205 /* DDR memory controllers per socket */
207 /* DDR channels per DDR memory controller */
209 /* DDR DIMMs per DDR memory channel */
211 /* Per DDR channel memory-mapped I/O size */
213 /* HBM memory controllers per socket */
215 /* HBM channels per HBM memory controller */
217 /* HBM DIMMs per HBM memory channel */
219 /* Per HBM channel memory-mapped I/O size */