Lines Matching +full:sdm845 +full:- +full:gpi +full:- +full:dma
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <linux/dma-mapping.h>
14 #include <linux/dma/qcom-gpi-dma.h>
18 #include "../virt-dma.h"
66 /* DMA TRE */
70 /* Register offsets from gpi-top */
183 /* GPII specific Global - Enable bit register */
188 /* GPII general interrupt - Enable bit register */
475 u32 max_gpii; /* maximum # of gpii instances available per gpi block */
502 void __iomem *regs; /* points to gpi top */
554 return ring->phys_addr + (addr - ring->base); in to_physical()
559 return ring->base + (addr - ring->phys_addr); in to_virtual()
572 /* gpi_write_reg_field - write to specific bit field */
586 void __iomem *addr = gpii->regs + offset; in gpi_update_reg()
597 gpi_update_reg(gpii, GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
599 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
601 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
603 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
605 gpi_update_reg(gpii, GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
607 gpi_update_reg(gpii, GPII_n_CNTXT_GPII_IRQ_EN_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
609 gpi_update_reg(gpii, GPII_n_CNTXT_INTSET_OFFS(gpii->gpii_id), in gpi_disable_interrupts()
612 gpii->cntxt_type_irq_msk = 0; in gpi_disable_interrupts()
613 devm_free_irq(gpii->gpi_dev->dev, gpii->irq, gpii); in gpi_disable_interrupts()
614 gpii->configured_irq = false; in gpi_disable_interrupts()
627 if (!gpii->configured_irq) { in gpi_config_interrupts()
628 ret = devm_request_irq(gpii->gpi_dev->dev, gpii->irq, in gpi_config_interrupts()
630 "gpi-dma", gpii); in gpi_config_interrupts()
632 dev_err(gpii->gpi_dev->dev, "error request irq:%d ret:%d\n", in gpi_config_interrupts()
633 gpii->irq, ret); in gpi_config_interrupts()
644 gpii->cntxt_type_irq_msk |= GPII_n_CNTXT_TYPE_IRQ_MSK_IEOB; in gpi_config_interrupts()
646 gpii->cntxt_type_irq_msk &= ~(GPII_n_CNTXT_TYPE_IRQ_MSK_IEOB); in gpi_config_interrupts()
647 gpi_update_reg(gpii, GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
648 GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK, gpii->cntxt_type_irq_msk); in gpi_config_interrupts()
650 gpi_update_reg(gpii, GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
652 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
655 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
658 gpi_update_reg(gpii, GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(gpii->gpii_id), in gpi_config_interrupts()
661 gpi_update_reg(gpii, GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(gpii->gpii_id), in gpi_config_interrupts()
664 gpi_update_reg(gpii, GPII_n_CNTXT_GPII_IRQ_EN_OFFS(gpii->gpii_id), in gpi_config_interrupts()
666 gpi_update_reg(gpii, GPII_n_CNTXT_MSI_BASE_LSB_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
667 gpi_update_reg(gpii, GPII_n_CNTXT_MSI_BASE_MSB_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
668 gpi_update_reg(gpii, GPII_n_CNTXT_SCRATCH_0_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
669 gpi_update_reg(gpii, GPII_n_CNTXT_SCRATCH_1_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
670 gpi_update_reg(gpii, GPII_n_CNTXT_INTSET_OFFS(gpii->gpii_id), in gpi_config_interrupts()
672 gpi_update_reg(gpii, GPII_n_ERROR_LOG_OFFS(gpii->gpii_id), U32_MAX, 0); in gpi_config_interrupts()
674 gpii->cntxt_type_irq_msk = enable; in gpi_config_interrupts()
677 gpii->configured_irq = true; in gpi_config_interrupts()
691 return -EINVAL; in gpi_send_cmd()
693 chid = gchan->chid; in gpi_send_cmd()
695 dev_dbg(gpii->gpi_dev->dev, in gpi_send_cmd()
699 reinit_completion(&gpii->cmd_completion); in gpi_send_cmd()
700 gpii->gpi_cmd = gpi_cmd; in gpi_send_cmd()
702 cmd_reg = IS_CHAN_CMD(gpi_cmd) ? gchan->ch_cmd_reg : gpii->ev_cmd_reg; in gpi_send_cmd()
706 timeout = wait_for_completion_timeout(&gpii->cmd_completion, in gpi_send_cmd()
709 dev_err(gpii->gpi_dev->dev, "cmd: %s completion timeout:%u\n", in gpi_send_cmd()
711 return -EIO; in gpi_send_cmd()
718 if (IS_CHAN_CMD(gpi_cmd) && gchan->ch_state == gpi_cmd_info[gpi_cmd].state) in gpi_send_cmd()
721 if (!IS_CHAN_CMD(gpi_cmd) && gpii->ev_state == gpi_cmd_info[gpi_cmd].state) in gpi_send_cmd()
724 return -EIO; in gpi_send_cmd()
731 struct gpii *gpii = gchan->gpii; in gpi_write_ch_db()
735 gpi_write_reg(gpii, gchan->ch_cntxt_db_reg, p_wp); in gpi_write_ch_db()
744 p_wp = ring->phys_addr + (wp - ring->base); in gpi_write_ev_db()
745 gpi_write_reg(gpii, gpii->ev_cntxt_db_reg, p_wp); in gpi_write_ev_db()
751 gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0)); in gpi_process_ieob()
754 tasklet_hi_schedule(&gpii->ev_task); in gpi_process_ieob()
760 u32 gpii_id = gpii->gpii_id; in gpi_process_ch_ctrl_irq()
762 u32 ch_irq = gpi_read_reg(gpii, gpii->regs + offset); in gpi_process_ch_ctrl_irq()
768 gpi_write_reg(gpii, gpii->regs + offset, (u32)ch_irq); in gpi_process_ch_ctrl_irq()
774 gchan = &gpii->gchan[chid]; in gpi_process_ch_ctrl_irq()
775 state = gpi_read_reg(gpii, gchan->ch_cntxt_base_reg + in gpi_process_ch_ctrl_irq()
784 if (gpii->gpi_cmd == GPI_CH_CMD_DE_ALLOC) in gpi_process_ch_ctrl_irq()
786 gchan->ch_state = state; in gpi_process_ch_ctrl_irq()
793 if (gchan->ch_state != CH_STATE_STOP_IN_PROC) in gpi_process_ch_ctrl_irq()
794 complete_all(&gpii->cmd_completion); in gpi_process_ch_ctrl_irq()
798 /* processing gpi general error interrupts */
801 u32 gpii_id = gpii->gpii_id; in gpi_process_gen_err_irq()
803 u32 irq_stts = gpi_read_reg(gpii, gpii->regs + offset); in gpi_process_gen_err_irq()
806 dev_dbg(gpii->gpi_dev->dev, "irq_stts:0x%x\n", irq_stts); in gpi_process_gen_err_irq()
810 gpi_write_reg(gpii, gpii->regs + offset, irq_stts); in gpi_process_gen_err_irq()
813 /* processing gpi level error interrupts */
816 u32 gpii_id = gpii->gpii_id; in gpi_process_glob_err_irq()
818 u32 irq_stts = gpi_read_reg(gpii, gpii->regs + offset); in gpi_process_glob_err_irq()
821 gpi_write_reg(gpii, gpii->regs + offset, irq_stts); in gpi_process_glob_err_irq()
825 dev_err(gpii->gpi_dev->dev, "invalid error status:0x%x\n", irq_stts); in gpi_process_glob_err_irq()
830 gpi_write_reg(gpii, gpii->regs + offset, 0); in gpi_process_glob_err_irq()
837 u32 gpii_id = gpii->gpii_id; in gpi_handle_irq()
841 read_lock_irqsave(&gpii->pm_lock, flags); in gpi_handle_irq()
847 if (!REG_ACCESS_VALID(gpii->pm_state)) { in gpi_handle_irq()
848 dev_err(gpii->gpi_dev->dev, "receive interrupt while in %s state\n", in gpi_handle_irq()
849 TO_GPI_PM_STR(gpii->pm_state)); in gpi_handle_irq()
853 offset = GPII_n_CNTXT_TYPE_IRQ_OFFS(gpii->gpii_id); in gpi_handle_irq()
854 type = gpi_read_reg(gpii, gpii->regs + offset); in gpi_handle_irq()
874 dev_dbg(gpii->gpi_dev->dev, in gpi_handle_irq()
877 ev_ch_irq = gpi_read_reg(gpii, gpii->regs + offset); in gpi_handle_irq()
881 gpi_write_reg(gpii, gpii->regs + offset, ev_ch_irq); in gpi_handle_irq()
882 ev_state = gpi_read_reg(gpii, gpii->ev_cntxt_base_reg + in gpi_handle_irq()
891 if (gpii->gpi_cmd == GPI_EV_CMD_DEALLOC) in gpi_handle_irq()
894 gpii->ev_state = ev_state; in gpi_handle_irq()
895 dev_dbg(gpii->gpi_dev->dev, "setting EV state to %s\n", in gpi_handle_irq()
896 TO_GPI_EV_STATE_STR(gpii->ev_state)); in gpi_handle_irq()
897 complete_all(&gpii->cmd_completion); in gpi_handle_irq()
903 dev_dbg(gpii->gpi_dev->dev, "process CH CTRL interrupts\n"); in gpi_handle_irq()
909 dev_err(gpii->gpi_dev->dev, "Unhandled interrupt status:0x%x\n", type); in gpi_handle_irq()
914 offset = GPII_n_CNTXT_TYPE_IRQ_OFFS(gpii->gpii_id); in gpi_handle_irq()
915 type = gpi_read_reg(gpii, gpii->regs + offset); in gpi_handle_irq()
919 read_unlock_irqrestore(&gpii->pm_lock, flags); in gpi_handle_irq()
924 /* process DMA Immediate completion data events */
928 struct gpii *gpii = gchan->gpii; in gpi_process_imed_data_event()
929 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_process_imed_data_event()
930 void *tre = ch_ring->base + (ch_ring->el_size * imed_event->tre_index); in gpi_process_imed_data_event()
940 if (gchan->pm_state != ACTIVE_STATE) { in gpi_process_imed_data_event()
941 dev_err(gpii->gpi_dev->dev, "skipping processing event because ch @ %s state\n", in gpi_process_imed_data_event()
942 TO_GPI_PM_STR(gchan->pm_state)); in gpi_process_imed_data_event()
946 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
947 vd = vchan_next_desc(&gchan->vc); in gpi_process_imed_data_event()
952 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
953 dev_dbg(gpii->gpi_dev->dev, "event without a pending descriptor!\n"); in gpi_process_imed_data_event()
955 dev_dbg(gpii->gpi_dev->dev, in gpi_process_imed_data_event()
957 gpi_ere->dword[0], gpi_ere->dword[1], in gpi_process_imed_data_event()
958 gpi_ere->dword[2], gpi_ere->dword[3]); in gpi_process_imed_data_event()
960 dev_dbg(gpii->gpi_dev->dev, in gpi_process_imed_data_event()
962 gpi_tre->dword[0], gpi_tre->dword[1], in gpi_process_imed_data_event()
963 gpi_tre->dword[2], gpi_tre->dword[3]); in gpi_process_imed_data_event()
967 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
973 tre += ch_ring->el_size; in gpi_process_imed_data_event()
974 if (tre >= (ch_ring->base + ch_ring->len)) in gpi_process_imed_data_event()
975 tre = ch_ring->base; in gpi_process_imed_data_event()
976 ch_ring->rp = tre; in gpi_process_imed_data_event()
981 chid = imed_event->chid; in gpi_process_imed_data_event()
982 if (imed_event->code == MSM_GPI_TCE_EOT && gpii->ieob_set) { in gpi_process_imed_data_event()
989 if (imed_event->code == MSM_GPI_TCE_UNEXP_ERR) in gpi_process_imed_data_event()
993 result.residue = gpi_desc->len - imed_event->length; in gpi_process_imed_data_event()
995 dma_cookie_complete(&vd->tx); in gpi_process_imed_data_event()
996 dmaengine_desc_get_callback_invoke(&vd->tx, &result); in gpi_process_imed_data_event()
999 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
1000 list_del(&vd->node); in gpi_process_imed_data_event()
1001 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_imed_data_event()
1010 struct gpii *gpii = gchan->gpii; in gpi_process_xfer_compl_event()
1011 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_process_xfer_compl_event()
1012 void *ev_rp = to_virtual(ch_ring, compl_event->ptr); in gpi_process_xfer_compl_event()
1020 if (unlikely(gchan->pm_state != ACTIVE_STATE)) { in gpi_process_xfer_compl_event()
1021 dev_err(gpii->gpi_dev->dev, "skipping processing event because ch @ %s state\n", in gpi_process_xfer_compl_event()
1022 TO_GPI_PM_STR(gchan->pm_state)); in gpi_process_xfer_compl_event()
1026 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1027 vd = vchan_next_desc(&gchan->vc); in gpi_process_xfer_compl_event()
1031 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1032 dev_err(gpii->gpi_dev->dev, "Event without a pending descriptor!\n"); in gpi_process_xfer_compl_event()
1034 dev_err(gpii->gpi_dev->dev, in gpi_process_xfer_compl_event()
1036 gpi_ere->dword[0], gpi_ere->dword[1], in gpi_process_xfer_compl_event()
1037 gpi_ere->dword[2], gpi_ere->dword[3]); in gpi_process_xfer_compl_event()
1042 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1048 ev_rp += ch_ring->el_size; in gpi_process_xfer_compl_event()
1049 if (ev_rp >= (ch_ring->base + ch_ring->len)) in gpi_process_xfer_compl_event()
1050 ev_rp = ch_ring->base; in gpi_process_xfer_compl_event()
1051 ch_ring->rp = ev_rp; in gpi_process_xfer_compl_event()
1056 chid = compl_event->chid; in gpi_process_xfer_compl_event()
1057 if (compl_event->code == MSM_GPI_TCE_EOT && gpii->ieob_set) { in gpi_process_xfer_compl_event()
1064 if (compl_event->code == MSM_GPI_TCE_UNEXP_ERR) { in gpi_process_xfer_compl_event()
1065 dev_err(gpii->gpi_dev->dev, "Error in Transaction\n"); in gpi_process_xfer_compl_event()
1068 dev_dbg(gpii->gpi_dev->dev, "Transaction Success\n"); in gpi_process_xfer_compl_event()
1071 result.residue = gpi_desc->len - compl_event->length; in gpi_process_xfer_compl_event()
1072 dev_dbg(gpii->gpi_dev->dev, "Residue %d\n", result.residue); in gpi_process_xfer_compl_event()
1074 dma_cookie_complete(&vd->tx); in gpi_process_xfer_compl_event()
1075 dmaengine_desc_get_callback_invoke(&vd->tx, &result); in gpi_process_xfer_compl_event()
1078 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1079 list_del(&vd->node); in gpi_process_xfer_compl_event()
1080 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_process_xfer_compl_event()
1088 struct gpi_ring *ev_ring = &gpii->ev_ring; in gpi_process_events()
1095 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_process_events()
1099 while (rp != ev_ring->rp) { in gpi_process_events()
1100 gpi_event = ev_ring->rp; in gpi_process_events()
1101 chid = gpi_event->xfer_compl_event.chid; in gpi_process_events()
1102 type = gpi_event->xfer_compl_event.type; in gpi_process_events()
1104 dev_dbg(gpii->gpi_dev->dev, in gpi_process_events()
1106 chid, type, gpi_event->gpi_ere.dword[0], in gpi_process_events()
1107 gpi_event->gpi_ere.dword[1], gpi_event->gpi_ere.dword[2], in gpi_process_events()
1108 gpi_event->gpi_ere.dword[3]); in gpi_process_events()
1112 gchan = &gpii->gchan[chid]; in gpi_process_events()
1114 &gpi_event->xfer_compl_event); in gpi_process_events()
1117 dev_dbg(gpii->gpi_dev->dev, "stale event, not processing\n"); in gpi_process_events()
1120 gchan = &gpii->gchan[chid]; in gpi_process_events()
1122 &gpi_event->immediate_data_event); in gpi_process_events()
1125 dev_dbg(gpii->gpi_dev->dev, "QUP_NOTIF_EV_TYPE\n"); in gpi_process_events()
1128 dev_dbg(gpii->gpi_dev->dev, in gpi_process_events()
1133 gpi_write_ev_db(gpii, ev_ring, ev_ring->wp); in gpi_process_events()
1136 gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0)); in gpi_process_events()
1138 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_process_events()
1141 } while (rp != ev_ring->rp); in gpi_process_events()
1149 read_lock(&gpii->pm_lock); in gpi_ev_tasklet()
1150 if (!REG_ACCESS_VALID(gpii->pm_state)) { in gpi_ev_tasklet()
1151 read_unlock(&gpii->pm_lock); in gpi_ev_tasklet()
1152 dev_err(gpii->gpi_dev->dev, "not processing any events, pm_state:%s\n", in gpi_ev_tasklet()
1153 TO_GPI_PM_STR(gpii->pm_state)); in gpi_ev_tasklet()
1162 read_unlock(&gpii->pm_lock); in gpi_ev_tasklet()
1168 struct gpii *gpii = gchan->gpii; in gpi_mark_stale_events()
1169 struct gpi_ring *ev_ring = &gpii->ev_ring; in gpi_mark_stale_events()
1173 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_mark_stale_events()
1175 ev_rp = ev_ring->rp; in gpi_mark_stale_events()
1179 u32 chid = gpi_event->xfer_compl_event.chid; in gpi_mark_stale_events()
1181 if (chid == gchan->chid) in gpi_mark_stale_events()
1182 gpi_event->xfer_compl_event.type = STALE_EV_TYPE; in gpi_mark_stale_events()
1183 ev_rp += ev_ring->el_size; in gpi_mark_stale_events()
1184 if (ev_rp >= (ev_ring->base + ev_ring->len)) in gpi_mark_stale_events()
1185 ev_rp = ev_ring->base; in gpi_mark_stale_events()
1186 cntxt_rp = gpi_read_reg(gpii, gpii->ev_ring_rp_lsb_reg); in gpi_mark_stale_events()
1191 /* reset sw state and issue channel reset or de-alloc */
1194 struct gpii *gpii = gchan->gpii; in gpi_reset_chan()
1195 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_reset_chan()
1201 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_reset_chan()
1207 ch_ring->rp = ch_ring->base; in gpi_reset_chan()
1208 ch_ring->wp = ch_ring->base; in gpi_reset_chan()
1214 write_lock_irq(&gpii->pm_lock); in gpi_reset_chan()
1218 spin_lock(&gchan->vc.lock); in gpi_reset_chan()
1219 vchan_get_all_descriptors(&gchan->vc, &list); in gpi_reset_chan()
1220 spin_unlock(&gchan->vc.lock); in gpi_reset_chan()
1221 write_unlock_irq(&gpii->pm_lock); in gpi_reset_chan()
1222 vchan_dma_desc_free_list(&gchan->vc, &list); in gpi_reset_chan()
1229 struct gpii *gpii = gchan->gpii; in gpi_start_chan()
1234 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_start_chan()
1240 write_lock_irq(&gpii->pm_lock); in gpi_start_chan()
1241 gchan->pm_state = ACTIVE_STATE; in gpi_start_chan()
1242 write_unlock_irq(&gpii->pm_lock); in gpi_start_chan()
1249 struct gpii *gpii = gchan->gpii; in gpi_stop_chan()
1254 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_stop_chan()
1265 struct gpii *gpii = chan->gpii; in gpi_alloc_chan()
1266 struct gpi_ring *ring = &chan->ch_ring; in gpi_alloc_chan()
1268 u32 id = gpii->gpii_id; in gpi_alloc_chan()
1269 u32 chid = chan->chid; in gpi_alloc_chan()
1275 dev_err(gpii->gpi_dev->dev, "Error with cmd:%s ret:%d\n", in gpi_alloc_chan()
1281 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_0_CONFIG, in gpi_alloc_chan()
1282 GPII_n_CH_k_CNTXT_0(ring->el_size, 0, chan->dir, GPI_CHTYPE_PROTO_GPI)); in gpi_alloc_chan()
1283 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_1_R_LENGTH, ring->len); in gpi_alloc_chan()
1284 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_2_RING_BASE_LSB, ring->phys_addr); in gpi_alloc_chan()
1285 gpi_write_reg(gpii, chan->ch_cntxt_base_reg + CNTXT_3_RING_BASE_MSB, in gpi_alloc_chan()
1286 upper_32_bits(ring->phys_addr)); in gpi_alloc_chan()
1287 gpi_write_reg(gpii, chan->ch_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB, in gpi_alloc_chan()
1288 upper_32_bits(ring->phys_addr)); in gpi_alloc_chan()
1289 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_0_OFFS(id, chid), in gpi_alloc_chan()
1290 GPII_n_CH_k_SCRATCH_0(pair_chid, chan->protocol, chan->seid)); in gpi_alloc_chan()
1291 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0); in gpi_alloc_chan()
1292 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), 0); in gpi_alloc_chan()
1293 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, chid), 0); in gpi_alloc_chan()
1294 gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_QOS_OFFS(id, chid), 1); in gpi_alloc_chan()
1304 struct gpi_ring *ring = &gpii->ev_ring; in gpi_alloc_ev_chan()
1305 void __iomem *base = gpii->ev_cntxt_base_reg; in gpi_alloc_ev_chan()
1310 dev_err(gpii->gpi_dev->dev, "error with cmd:%s ret:%d\n", in gpi_alloc_ev_chan()
1317 GPII_n_EV_k_CNTXT_0(ring->el_size, GPI_INTTYPE_IRQ, GPI_CHTYPE_GPI_EV)); in gpi_alloc_ev_chan()
1318 gpi_write_reg(gpii, base + CNTXT_1_R_LENGTH, ring->len); in gpi_alloc_ev_chan()
1319 gpi_write_reg(gpii, base + CNTXT_2_RING_BASE_LSB, lower_32_bits(ring->phys_addr)); in gpi_alloc_ev_chan()
1320 gpi_write_reg(gpii, base + CNTXT_3_RING_BASE_MSB, upper_32_bits(ring->phys_addr)); in gpi_alloc_ev_chan()
1321 gpi_write_reg(gpii, gpii->ev_cntxt_db_reg + CNTXT_5_RING_RP_MSB - CNTXT_4_RING_RP_LSB, in gpi_alloc_ev_chan()
1322 upper_32_bits(ring->phys_addr)); in gpi_alloc_ev_chan()
1331 ring->wp = (ring->base + ring->len - ring->el_size); in gpi_alloc_ev_chan()
1337 write_lock_irq(&gpii->pm_lock); in gpi_alloc_ev_chan()
1338 gpii->pm_state = ACTIVE_STATE; in gpi_alloc_ev_chan()
1339 write_unlock_irq(&gpii->pm_lock); in gpi_alloc_ev_chan()
1340 gpi_write_ev_db(gpii, ring, ring->wp); in gpi_alloc_ev_chan()
1350 if (ring->wp < ring->rp) { in gpi_ring_num_elements_avail()
1351 elements = ((ring->rp - ring->wp) / ring->el_size) - 1; in gpi_ring_num_elements_avail()
1353 elements = (ring->rp - ring->base) / ring->el_size; in gpi_ring_num_elements_avail()
1354 elements += ((ring->base + ring->len - ring->wp) / ring->el_size) - 1; in gpi_ring_num_elements_avail()
1363 return -ENOMEM; in gpi_ring_add_element()
1365 *wp = ring->wp; in gpi_ring_add_element()
1366 ring->wp += ring->el_size; in gpi_ring_add_element()
1367 if (ring->wp >= (ring->base + ring->len)) in gpi_ring_add_element()
1368 ring->wp = ring->base; in gpi_ring_add_element()
1379 ring->wp += ring->el_size; in gpi_ring_recycle_ev_element()
1380 if (ring->wp >= (ring->base + ring->len)) in gpi_ring_recycle_ev_element()
1381 ring->wp = ring->base; in gpi_ring_recycle_ev_element()
1384 ring->rp += ring->el_size; in gpi_ring_recycle_ev_element()
1385 if (ring->rp >= (ring->base + ring->len)) in gpi_ring_recycle_ev_element()
1386 ring->rp = ring->base; in gpi_ring_recycle_ev_element()
1395 dma_free_coherent(gpii->gpi_dev->dev, ring->alloc_size, in gpi_free_ring()
1396 ring->pre_aligned, ring->dma_handle); in gpi_free_ring()
1409 if (((1 << bit) - 1) & len) in gpi_alloc_ring()
1412 ring->alloc_size = (len + (len - 1)); in gpi_alloc_ring()
1413 dev_dbg(gpii->gpi_dev->dev, in gpi_alloc_ring()
1416 ring->alloc_size); in gpi_alloc_ring()
1418 ring->pre_aligned = dma_alloc_coherent(gpii->gpi_dev->dev, in gpi_alloc_ring()
1419 ring->alloc_size, in gpi_alloc_ring()
1420 &ring->dma_handle, GFP_KERNEL); in gpi_alloc_ring()
1421 if (!ring->pre_aligned) { in gpi_alloc_ring()
1422 dev_err(gpii->gpi_dev->dev, "could not alloc size:%zu mem for ring\n", in gpi_alloc_ring()
1423 ring->alloc_size); in gpi_alloc_ring()
1424 return -ENOMEM; in gpi_alloc_ring()
1428 ring->phys_addr = (ring->dma_handle + (len - 1)) & ~(len - 1); in gpi_alloc_ring()
1429 ring->base = ring->pre_aligned + (ring->phys_addr - ring->dma_handle); in gpi_alloc_ring()
1430 ring->rp = ring->base; in gpi_alloc_ring()
1431 ring->wp = ring->base; in gpi_alloc_ring()
1432 ring->len = len; in gpi_alloc_ring()
1433 ring->el_size = el_size; in gpi_alloc_ring()
1434 ring->elements = ring->len / ring->el_size; in gpi_alloc_ring()
1435 memset(ring->base, 0, ring->len); in gpi_alloc_ring()
1436 ring->configured = true; in gpi_alloc_ring()
1441 dev_dbg(gpii->gpi_dev->dev, in gpi_alloc_ring()
1443 &ring->dma_handle, &ring->phys_addr, ring->len, in gpi_alloc_ring()
1444 ring->el_size, ring->elements); in gpi_alloc_ring()
1457 ret = gpi_ring_add_element(&gchan->ch_ring, (void **)&ch_tre); in gpi_queue_xfer()
1459 dev_err(gpii->gpi_dev->dev, "Error adding ring element to xfer ring\n"); in gpi_queue_xfer()
1472 struct gpii *gpii = gchan->gpii; in gpi_terminate_all()
1476 mutex_lock(&gpii->ctrl_lock); in gpi_terminate_all()
1482 schid = (gchan->protocol == QCOM_GPI_UART) ? gchan->chid : 0; in gpi_terminate_all()
1483 echid = (gchan->protocol == QCOM_GPI_UART) ? schid + 1 : MAX_CHANNELS_PER_GPII; in gpi_terminate_all()
1487 gchan = &gpii->gchan[i]; in gpi_terminate_all()
1490 write_lock_irq(&gpii->pm_lock); in gpi_terminate_all()
1491 gchan->pm_state = PREPARE_TERMINATE; in gpi_terminate_all()
1492 write_unlock_irq(&gpii->pm_lock); in gpi_terminate_all()
1500 gchan = &gpii->gchan[i]; in gpi_terminate_all()
1504 dev_err(gpii->gpi_dev->dev, "Error resetting channel ret:%d\n", ret); in gpi_terminate_all()
1511 dev_err(gpii->gpi_dev->dev, "Error alloc_channel ret:%d\n", ret); in gpi_terminate_all()
1518 gchan = &gpii->gchan[i]; in gpi_terminate_all()
1522 dev_err(gpii->gpi_dev->dev, "Error Starting Channel ret:%d\n", ret); in gpi_terminate_all()
1528 mutex_unlock(&gpii->ctrl_lock); in gpi_terminate_all()
1532 /* pause dma transfer for all channels */
1536 struct gpii *gpii = gchan->gpii; in gpi_pause()
1539 mutex_lock(&gpii->ctrl_lock); in gpi_pause()
1545 if (gpii->pm_state == PAUSE_STATE) { in gpi_pause()
1546 dev_dbg(gpii->gpi_dev->dev, "channel is already paused\n"); in gpi_pause()
1547 mutex_unlock(&gpii->ctrl_lock); in gpi_pause()
1553 ret = gpi_stop_chan(&gpii->gchan[i]); in gpi_pause()
1555 mutex_unlock(&gpii->ctrl_lock); in gpi_pause()
1560 disable_irq(gpii->irq); in gpi_pause()
1563 tasklet_kill(&gpii->ev_task); in gpi_pause()
1565 write_lock_irq(&gpii->pm_lock); in gpi_pause()
1566 gpii->pm_state = PAUSE_STATE; in gpi_pause()
1567 write_unlock_irq(&gpii->pm_lock); in gpi_pause()
1568 mutex_unlock(&gpii->ctrl_lock); in gpi_pause()
1573 /* resume dma transfer */
1577 struct gpii *gpii = gchan->gpii; in gpi_resume()
1580 mutex_lock(&gpii->ctrl_lock); in gpi_resume()
1581 if (gpii->pm_state == ACTIVE_STATE) { in gpi_resume()
1582 dev_dbg(gpii->gpi_dev->dev, "channel is already active\n"); in gpi_resume()
1583 mutex_unlock(&gpii->ctrl_lock); in gpi_resume()
1587 enable_irq(gpii->irq); in gpi_resume()
1591 ret = gpi_send_cmd(gpii, &gpii->gchan[i], GPI_CH_CMD_START); in gpi_resume()
1593 dev_err(gpii->gpi_dev->dev, "Error starting chan, ret:%d\n", ret); in gpi_resume()
1594 mutex_unlock(&gpii->ctrl_lock); in gpi_resume()
1599 write_lock_irq(&gpii->pm_lock); in gpi_resume()
1600 gpii->pm_state = ACTIVE_STATE; in gpi_resume()
1601 write_unlock_irq(&gpii->pm_lock); in gpi_resume()
1602 mutex_unlock(&gpii->ctrl_lock); in gpi_resume()
1620 if (!config->peripheral_config) in gpi_peripheral_config()
1621 return -EINVAL; in gpi_peripheral_config()
1623 gchan->config = krealloc(gchan->config, config->peripheral_size, GFP_NOWAIT); in gpi_peripheral_config()
1624 if (!gchan->config) in gpi_peripheral_config()
1625 return -ENOMEM; in gpi_peripheral_config()
1627 memcpy(gchan->config, config->peripheral_config, config->peripheral_size); in gpi_peripheral_config()
1635 struct gpi_i2c_config *i2c = chan->config; in gpi_create_i2c_tre()
1636 struct device *dev = chan->gpii->gpi_dev->dev; in gpi_create_i2c_tre()
1643 if (i2c->set_config) { in gpi_create_i2c_tre()
1644 tre = &desc->tre[tre_idx]; in gpi_create_i2c_tre()
1647 tre->dword[0] = u32_encode_bits(i2c->low_count, TRE_I2C_C0_TLOW); in gpi_create_i2c_tre()
1648 tre->dword[0] |= u32_encode_bits(i2c->high_count, TRE_I2C_C0_THIGH); in gpi_create_i2c_tre()
1649 tre->dword[0] |= u32_encode_bits(i2c->cycle_count, TRE_I2C_C0_TCYL); in gpi_create_i2c_tre()
1650 tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_TX_PACK); in gpi_create_i2c_tre()
1651 tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_RX_PACK); in gpi_create_i2c_tre()
1653 tre->dword[1] = 0; in gpi_create_i2c_tre()
1655 tre->dword[2] = u32_encode_bits(i2c->clk_div, TRE_C0_CLK_DIV); in gpi_create_i2c_tre()
1657 tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE); in gpi_create_i2c_tre()
1658 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_i2c_tre()
1662 if (i2c->op == I2C_WRITE) { in gpi_create_i2c_tre()
1663 tre = &desc->tre[tre_idx]; in gpi_create_i2c_tre()
1666 if (i2c->multi_msg) in gpi_create_i2c_tre()
1667 tre->dword[0] = u32_encode_bits(I2C_READ, TRE_I2C_GO_CMD); in gpi_create_i2c_tre()
1669 tre->dword[0] = u32_encode_bits(i2c->op, TRE_I2C_GO_CMD); in gpi_create_i2c_tre()
1671 tre->dword[0] |= u32_encode_bits(i2c->addr, TRE_I2C_GO_ADDR); in gpi_create_i2c_tre()
1672 tre->dword[0] |= u32_encode_bits(i2c->stretch, TRE_I2C_GO_STRETCH); in gpi_create_i2c_tre()
1674 tre->dword[1] = 0; in gpi_create_i2c_tre()
1675 tre->dword[2] = u32_encode_bits(i2c->rx_len, TRE_RX_LEN); in gpi_create_i2c_tre()
1677 tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE); in gpi_create_i2c_tre()
1679 if (i2c->multi_msg) in gpi_create_i2c_tre()
1680 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); in gpi_create_i2c_tre()
1682 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_i2c_tre()
1685 if (i2c->op == I2C_READ || i2c->multi_msg == false) { in gpi_create_i2c_tre()
1686 /* create the DMA TRE */ in gpi_create_i2c_tre()
1687 tre = &desc->tre[tre_idx]; in gpi_create_i2c_tre()
1691 tre->dword[0] = lower_32_bits(address); in gpi_create_i2c_tre()
1692 tre->dword[1] = upper_32_bits(address); in gpi_create_i2c_tre()
1694 tre->dword[2] = u32_encode_bits(sg_dma_len(sgl), TRE_DMA_LEN); in gpi_create_i2c_tre()
1696 tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); in gpi_create_i2c_tre()
1697 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); in gpi_create_i2c_tre()
1701 dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], in gpi_create_i2c_tre()
1702 desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); in gpi_create_i2c_tre()
1710 struct gpi_spi_config *spi = chan->config; in gpi_create_spi_tre()
1711 struct device *dev = chan->gpii->gpi_dev->dev; in gpi_create_spi_tre()
1719 if (direction == DMA_MEM_TO_DEV && spi->set_config) { in gpi_create_spi_tre()
1720 tre = &desc->tre[tre_idx]; in gpi_create_spi_tre()
1723 tre->dword[0] = u32_encode_bits(spi->word_len, TRE_SPI_C0_WORD_SZ); in gpi_create_spi_tre()
1724 tre->dword[0] |= u32_encode_bits(spi->loopback_en, TRE_SPI_C0_LOOPBACK); in gpi_create_spi_tre()
1725 tre->dword[0] |= u32_encode_bits(spi->clock_pol_high, TRE_SPI_C0_CPOL); in gpi_create_spi_tre()
1726 tre->dword[0] |= u32_encode_bits(spi->data_pol_high, TRE_SPI_C0_CPHA); in gpi_create_spi_tre()
1727 tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_TX_PACK); in gpi_create_spi_tre()
1728 tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_RX_PACK); in gpi_create_spi_tre()
1730 tre->dword[1] = 0; in gpi_create_spi_tre()
1732 tre->dword[2] = u32_encode_bits(spi->clk_div, TRE_C0_CLK_DIV); in gpi_create_spi_tre()
1733 tre->dword[2] |= u32_encode_bits(spi->clk_src, TRE_C0_CLK_SRC); in gpi_create_spi_tre()
1735 tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1736 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_spi_tre()
1741 tre = &desc->tre[tre_idx]; in gpi_create_spi_tre()
1744 tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG); in gpi_create_spi_tre()
1745 tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS); in gpi_create_spi_tre()
1746 tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD); in gpi_create_spi_tre()
1748 tre->dword[1] = 0; in gpi_create_spi_tre()
1750 tre->dword[2] = u32_encode_bits(spi->rx_len, TRE_RX_LEN); in gpi_create_spi_tre()
1752 tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1753 if (spi->cmd == SPI_RX) { in gpi_create_spi_tre()
1754 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB); in gpi_create_spi_tre()
1755 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); in gpi_create_spi_tre()
1756 } else if (spi->cmd == SPI_TX) { in gpi_create_spi_tre()
1757 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_spi_tre()
1759 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN); in gpi_create_spi_tre()
1760 tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK); in gpi_create_spi_tre()
1764 /* create the dma tre */ in gpi_create_spi_tre()
1765 tre = &desc->tre[tre_idx]; in gpi_create_spi_tre()
1771 /* Support Immediate dma for write transfers for data length up to 8 bytes */ in gpi_create_spi_tre()
1772 if (direction == DMA_MEM_TO_DEV && len <= 2 * sizeof(tre->dword[0])) { in gpi_create_spi_tre()
1774 * For Immediate dma, data length may not always be length of 8 bytes, in gpi_create_spi_tre()
1777 tre->dword[0] = 0; in gpi_create_spi_tre()
1778 tre->dword[1] = 0; in gpi_create_spi_tre()
1779 memcpy(&tre->dword[0], sg_virt(sgl), len); in gpi_create_spi_tre()
1781 tre->dword[2] = u32_encode_bits(len, TRE_DMA_IMMEDIATE_LEN); in gpi_create_spi_tre()
1782 tre->dword[3] = u32_encode_bits(TRE_TYPE_IMMEDIATE_DMA, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1784 tre->dword[0] = lower_32_bits(address); in gpi_create_spi_tre()
1785 tre->dword[1] = upper_32_bits(address); in gpi_create_spi_tre()
1787 tre->dword[2] = u32_encode_bits(len, TRE_DMA_LEN); in gpi_create_spi_tre()
1788 tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); in gpi_create_spi_tre()
1791 tre->dword[3] |= u32_encode_bits(direction == DMA_MEM_TO_DEV, in gpi_create_spi_tre()
1795 dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], in gpi_create_spi_tre()
1796 desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); in gpi_create_spi_tre()
1808 struct gpii *gpii = gchan->gpii; in gpi_prep_slave_sg()
1809 struct device *dev = gpii->gpi_dev->dev; in gpi_prep_slave_sg()
1810 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_prep_slave_sg()
1816 gpii->ieob_set = false; in gpi_prep_slave_sg()
1818 dev_err(gpii->gpi_dev->dev, "invalid dma direction: %d\n", direction); in gpi_prep_slave_sg()
1828 set_config = *(u32 *)gchan->config; in gpi_prep_slave_sg()
1846 if (gchan->protocol == QCOM_GPI_SPI) { in gpi_prep_slave_sg()
1848 } else if (gchan->protocol == QCOM_GPI_I2C) { in gpi_prep_slave_sg()
1851 dev_err(dev, "invalid peripheral: %d\n", gchan->protocol); in gpi_prep_slave_sg()
1857 gpi_desc->gchan = gchan; in gpi_prep_slave_sg()
1858 gpi_desc->len = sg_dma_len(sgl); in gpi_prep_slave_sg()
1859 gpi_desc->num_tre = i; in gpi_prep_slave_sg()
1861 return vchan_tx_prep(&gchan->vc, &gpi_desc->vd, flags); in gpi_prep_slave_sg()
1868 struct gpii *gpii = gchan->gpii; in gpi_issue_pending()
1872 struct gpi_ring *ch_ring = &gchan->ch_ring; in gpi_issue_pending()
1876 read_lock_irqsave(&gpii->pm_lock, pm_lock_flags); in gpi_issue_pending()
1879 spin_lock_irqsave(&gchan->vc.lock, flags); in gpi_issue_pending()
1880 if (vchan_issue_pending(&gchan->vc)) in gpi_issue_pending()
1881 vd = list_last_entry(&gchan->vc.desc_issued, in gpi_issue_pending()
1883 spin_unlock_irqrestore(&gchan->vc.lock, flags); in gpi_issue_pending()
1887 read_unlock_irqrestore(&gpii->pm_lock, pm_lock_flags); in gpi_issue_pending()
1892 for (i = 0; i < gpi_desc->num_tre; i++) { in gpi_issue_pending()
1893 tre = &gpi_desc->tre[i]; in gpi_issue_pending()
1897 gpi_desc->db = ch_ring->wp; in gpi_issue_pending()
1898 gpi_write_ch_db(gchan, &gchan->ch_ring, gpi_desc->db); in gpi_issue_pending()
1899 read_unlock_irqrestore(&gpii->pm_lock, pm_lock_flags); in gpi_issue_pending()
1904 struct gpii *gpii = gchan->gpii; in gpi_ch_init()
1905 const int ev_factor = gpii->gpi_dev->ev_factor; in gpi_ch_init()
1909 gchan->pm_state = CONFIG_STATE; in gpi_ch_init()
1913 if (gpii->gchan[i].pm_state != CONFIG_STATE) in gpi_ch_init()
1917 if (gpii->gchan[0].protocol != gpii->gchan[1].protocol) { in gpi_ch_init()
1918 dev_err(gpii->gpi_dev->dev, "protocol did not match protocol %u != %u\n", in gpi_ch_init()
1919 gpii->gchan[0].protocol, gpii->gchan[1].protocol); in gpi_ch_init()
1920 ret = -EINVAL; in gpi_ch_init()
1926 ret = gpi_alloc_ring(&gpii->ev_ring, elements, in gpi_ch_init()
1932 write_lock_irq(&gpii->pm_lock); in gpi_ch_init()
1933 gpii->pm_state = PREPARE_HARDWARE; in gpi_ch_init()
1934 write_unlock_irq(&gpii->pm_lock); in gpi_ch_init()
1937 dev_err(gpii->gpi_dev->dev, "error config. interrupts, ret:%d\n", ret); in gpi_ch_init()
1944 dev_err(gpii->gpi_dev->dev, "error alloc_ev_chan:%d\n", ret); in gpi_ch_init()
1950 ret = gpi_alloc_chan(&gpii->gchan[i], true); in gpi_ch_init()
1952 dev_err(gpii->gpi_dev->dev, "Error allocating chan:%d\n", ret); in gpi_ch_init()
1959 ret = gpi_start_chan(&gpii->gchan[i]); in gpi_ch_init()
1961 dev_err(gpii->gpi_dev->dev, "Error start chan:%d\n", ret); in gpi_ch_init()
1968 for (i = i - 1; i >= 0; i--) { in gpi_ch_init()
1969 gpi_stop_chan(&gpii->gchan[i]); in gpi_ch_init()
1974 for (i = i - 1; i >= 0; i--) in gpi_ch_init()
1979 gpi_free_ring(&gpii->ev_ring, gpii); in gpi_ch_init()
1988 struct gpii *gpii = gchan->gpii; in gpi_free_chan_resources()
1992 mutex_lock(&gpii->ctrl_lock); in gpi_free_chan_resources()
1994 cur_state = gchan->pm_state; in gpi_free_chan_resources()
1997 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
1998 gchan->pm_state = PREPARE_TERMINATE; in gpi_free_chan_resources()
1999 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2007 dev_err(gpii->gpi_dev->dev, "error resetting channel:%d\n", ret); in gpi_free_chan_resources()
2013 gpi_free_ring(&gchan->ch_ring, gpii); in gpi_free_chan_resources()
2014 vchan_free_chan_resources(&gchan->vc); in gpi_free_chan_resources()
2015 kfree(gchan->config); in gpi_free_chan_resources()
2017 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2018 gchan->pm_state = DISABLE_STATE; in gpi_free_chan_resources()
2019 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2023 if (gpii->gchan[i].ch_ring.configured) in gpi_free_chan_resources()
2027 cur_state = gpii->pm_state; in gpi_free_chan_resources()
2028 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2029 gpii->pm_state = PREPARE_TERMINATE; in gpi_free_chan_resources()
2030 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2033 tasklet_kill(&gpii->ev_task); in gpi_free_chan_resources()
2039 gpi_free_ring(&gpii->ev_ring, gpii); in gpi_free_chan_resources()
2046 write_lock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2047 gpii->pm_state = DISABLE_STATE; in gpi_free_chan_resources()
2048 write_unlock_irq(&gpii->pm_lock); in gpi_free_chan_resources()
2051 mutex_unlock(&gpii->ctrl_lock); in gpi_free_chan_resources()
2058 struct gpii *gpii = gchan->gpii; in gpi_alloc_chan_resources()
2061 mutex_lock(&gpii->ctrl_lock); in gpi_alloc_chan_resources()
2064 ret = gpi_alloc_ring(&gchan->ch_ring, CHAN_TRES, in gpi_alloc_chan_resources()
2071 mutex_unlock(&gpii->ctrl_lock); in gpi_alloc_chan_resources()
2075 mutex_unlock(&gpii->ctrl_lock); in gpi_alloc_chan_resources()
2086 for (gpii = 0; gpii < gpi_dev->max_gpii; gpii++) { in gpi_find_avail_gpii()
2087 if (!((1 << gpii) & gpi_dev->gpii_mask)) in gpi_find_avail_gpii()
2090 tx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_TX_CHAN]; in gpi_find_avail_gpii()
2091 rx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_RX_CHAN]; in gpi_find_avail_gpii()
2093 if (rx_chan->vc.chan.client_count && rx_chan->seid == seid) in gpi_find_avail_gpii()
2095 if (tx_chan->vc.chan.client_count && tx_chan->seid == seid) in gpi_find_avail_gpii()
2100 for (gpii = 0; gpii < gpi_dev->max_gpii; gpii++) { in gpi_find_avail_gpii()
2101 if (!((1 << gpii) & gpi_dev->gpii_mask)) in gpi_find_avail_gpii()
2104 tx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_TX_CHAN]; in gpi_find_avail_gpii()
2105 rx_chan = &gpi_dev->gpiis[gpii].gchan[GPI_RX_CHAN]; in gpi_find_avail_gpii()
2108 if (tx_chan->vc.chan.client_count || in gpi_find_avail_gpii()
2109 rx_chan->vc.chan.client_count) in gpi_find_avail_gpii()
2117 return -EIO; in gpi_find_avail_gpii()
2124 struct gpi_dev *gpi_dev = (struct gpi_dev *)of_dma->of_dma_data; in gpi_of_dma_xlate()
2129 if (args->args_count < 3) { in gpi_of_dma_xlate()
2130 dev_err(gpi_dev->dev, "gpii require minimum 2 args, client passed:%d args\n", in gpi_of_dma_xlate()
2131 args->args_count); in gpi_of_dma_xlate()
2135 chid = args->args[0]; in gpi_of_dma_xlate()
2137 dev_err(gpi_dev->dev, "gpii channel:%d not valid\n", chid); in gpi_of_dma_xlate()
2141 seid = args->args[1]; in gpi_of_dma_xlate()
2146 dev_err(gpi_dev->dev, "no available gpii instances\n"); in gpi_of_dma_xlate()
2150 gchan = &gpi_dev->gpiis[gpii].gchan[chid]; in gpi_of_dma_xlate()
2151 if (gchan->vc.chan.client_count) { in gpi_of_dma_xlate()
2152 dev_err(gpi_dev->dev, "gpii:%d chid:%d seid:%d already configured\n", in gpi_of_dma_xlate()
2153 gpii, chid, gchan->seid); in gpi_of_dma_xlate()
2157 gchan->seid = seid; in gpi_of_dma_xlate()
2158 gchan->protocol = args->args[2]; in gpi_of_dma_xlate()
2160 return dma_get_slave_channel(&gchan->vc.chan); in gpi_of_dma_xlate()
2170 gpi_dev = devm_kzalloc(&pdev->dev, sizeof(*gpi_dev), GFP_KERNEL); in gpi_probe()
2172 return -ENOMEM; in gpi_probe()
2174 gpi_dev->dev = &pdev->dev; in gpi_probe()
2175 gpi_dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &gpi_dev->res); in gpi_probe()
2176 if (IS_ERR(gpi_dev->regs)) in gpi_probe()
2177 return PTR_ERR(gpi_dev->regs); in gpi_probe()
2178 gpi_dev->ee_base = gpi_dev->regs; in gpi_probe()
2180 ret = of_property_read_u32(gpi_dev->dev->of_node, "dma-channels", in gpi_probe()
2181 &gpi_dev->max_gpii); in gpi_probe()
2183 dev_err(gpi_dev->dev, "missing 'max-no-gpii' DT node\n"); in gpi_probe()
2187 ret = of_property_read_u32(gpi_dev->dev->of_node, "dma-channel-mask", in gpi_probe()
2188 &gpi_dev->gpii_mask); in gpi_probe()
2190 dev_err(gpi_dev->dev, "missing 'gpii-mask' DT node\n"); in gpi_probe()
2194 ee_offset = (uintptr_t)device_get_match_data(gpi_dev->dev); in gpi_probe()
2195 gpi_dev->ee_base = gpi_dev->ee_base - ee_offset; in gpi_probe()
2197 gpi_dev->ev_factor = EV_FACTOR; in gpi_probe()
2199 ret = dma_set_mask(gpi_dev->dev, DMA_BIT_MASK(64)); in gpi_probe()
2201 dev_err(gpi_dev->dev, "Error setting dma_mask to 64, ret:%d\n", ret); in gpi_probe()
2205 gpi_dev->gpiis = devm_kzalloc(gpi_dev->dev, sizeof(*gpi_dev->gpiis) * in gpi_probe()
2206 gpi_dev->max_gpii, GFP_KERNEL); in gpi_probe()
2207 if (!gpi_dev->gpiis) in gpi_probe()
2208 return -ENOMEM; in gpi_probe()
2211 INIT_LIST_HEAD(&gpi_dev->dma_device.channels); in gpi_probe()
2212 for (i = 0; i < gpi_dev->max_gpii; i++) { in gpi_probe()
2213 struct gpii *gpii = &gpi_dev->gpiis[i]; in gpi_probe()
2216 if (!((1 << i) & gpi_dev->gpii_mask)) in gpi_probe()
2220 gpii->ev_cntxt_base_reg = gpi_dev->ee_base + GPII_n_EV_CH_k_CNTXT_0_OFFS(i, 0); in gpi_probe()
2221 gpii->ev_cntxt_db_reg = gpi_dev->ee_base + GPII_n_EV_CH_k_DOORBELL_0_OFFS(i, 0); in gpi_probe()
2222 gpii->ev_ring_rp_lsb_reg = gpii->ev_cntxt_base_reg + CNTXT_4_RING_RP_LSB; in gpi_probe()
2223 gpii->ev_cmd_reg = gpi_dev->ee_base + GPII_n_EV_CH_CMD_OFFS(i); in gpi_probe()
2224 gpii->ieob_clr_reg = gpi_dev->ee_base + GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(i); in gpi_probe()
2230 gpii->irq = ret; in gpi_probe()
2234 struct gchan *gchan = &gpii->gchan[chan]; in gpi_probe()
2237 gchan->ch_cntxt_base_reg = gpi_dev->ee_base + in gpi_probe()
2239 gchan->ch_cntxt_db_reg = gpi_dev->ee_base + in gpi_probe()
2241 gchan->ch_cmd_reg = gpi_dev->ee_base + GPII_n_CH_CMD_OFFS(i); in gpi_probe()
2244 vchan_init(&gchan->vc, &gpi_dev->dma_device); in gpi_probe()
2245 gchan->vc.desc_free = gpi_desc_free; in gpi_probe()
2246 gchan->chid = chan; in gpi_probe()
2247 gchan->gpii = gpii; in gpi_probe()
2248 gchan->dir = GPII_CHAN_DIR[chan]; in gpi_probe()
2250 mutex_init(&gpii->ctrl_lock); in gpi_probe()
2251 rwlock_init(&gpii->pm_lock); in gpi_probe()
2252 tasklet_init(&gpii->ev_task, gpi_ev_tasklet, in gpi_probe()
2254 init_completion(&gpii->cmd_completion); in gpi_probe()
2255 gpii->gpii_id = i; in gpi_probe()
2256 gpii->regs = gpi_dev->ee_base; in gpi_probe()
2257 gpii->gpi_dev = gpi_dev; in gpi_probe()
2263 dma_cap_zero(gpi_dev->dma_device.cap_mask); in gpi_probe()
2264 dma_cap_set(DMA_SLAVE, gpi_dev->dma_device.cap_mask); in gpi_probe()
2267 gpi_dev->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in gpi_probe()
2268 gpi_dev->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in gpi_probe()
2269 gpi_dev->dma_device.src_addr_widths = DMA_SLAVE_BUSWIDTH_8_BYTES; in gpi_probe()
2270 gpi_dev->dma_device.dst_addr_widths = DMA_SLAVE_BUSWIDTH_8_BYTES; in gpi_probe()
2271 gpi_dev->dma_device.device_alloc_chan_resources = gpi_alloc_chan_resources; in gpi_probe()
2272 gpi_dev->dma_device.device_free_chan_resources = gpi_free_chan_resources; in gpi_probe()
2273 gpi_dev->dma_device.device_tx_status = dma_cookie_status; in gpi_probe()
2274 gpi_dev->dma_device.device_issue_pending = gpi_issue_pending; in gpi_probe()
2275 gpi_dev->dma_device.device_prep_slave_sg = gpi_prep_slave_sg; in gpi_probe()
2276 gpi_dev->dma_device.device_config = gpi_peripheral_config; in gpi_probe()
2277 gpi_dev->dma_device.device_terminate_all = gpi_terminate_all; in gpi_probe()
2278 gpi_dev->dma_device.dev = gpi_dev->dev; in gpi_probe()
2279 gpi_dev->dma_device.device_pause = gpi_pause; in gpi_probe()
2280 gpi_dev->dma_device.device_resume = gpi_resume; in gpi_probe()
2283 ret = dma_async_device_register(&gpi_dev->dma_device); in gpi_probe()
2285 dev_err(gpi_dev->dev, "async_device_register failed ret:%d", ret); in gpi_probe()
2289 ret = of_dma_controller_register(gpi_dev->dev->of_node, in gpi_probe()
2292 dev_err(gpi_dev->dev, "of_dma_controller_reg failed ret:%d", ret); in gpi_probe()
2300 { .compatible = "qcom,sdm845-gpi-dma", .data = (void *)0x0 },
2301 { .compatible = "qcom,sm6350-gpi-dma", .data = (void *)0x10000 },
2304 * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma
2307 { .compatible = "qcom,sc7280-gpi-dma", .data = (void *)0x10000 },
2308 { .compatible = "qcom,sm8150-gpi-dma", .data = (void *)0x0 },
2309 { .compatible = "qcom,sm8250-gpi-dma", .data = (void *)0x0 },
2310 { .compatible = "qcom,sm8350-gpi-dma", .data = (void *)0x10000 },
2311 { .compatible = "qcom,sm8450-gpi-dma", .data = (void *)0x10000 },
2330 MODULE_DESCRIPTION("QCOM GPI DMA engine driver");