Lines Matching +full:0 +full:x10a00000
25 /* Register Offset definitions for CMU_TOP (0x1a330000) */
26 #define PLL_LOCKTIME_PLL_G3D 0x0000
27 #define PLL_LOCKTIME_PLL_MMC 0x0004
28 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
29 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
30 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
31 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
32 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
33 #define PLL_CON0_PLL_G3D 0x0100
34 #define PLL_CON3_PLL_G3D 0x010c
35 #define PLL_CON0_PLL_MMC 0x0140
36 #define PLL_CON3_PLL_MMC 0x014c
37 #define PLL_CON0_PLL_SHARED0 0x0180
38 #define PLL_CON3_PLL_SHARED0 0x018c
39 #define PLL_CON0_PLL_SHARED1 0x01c0
40 #define PLL_CON3_PLL_SHARED1 0x01cc
41 #define PLL_CON0_PLL_SHARED2 0x0200
42 #define PLL_CON3_PLL_SHARED2 0x020c
43 #define PLL_CON0_PLL_SHARED3 0x0240
44 #define PLL_CON3_PLL_SHARED3 0x024c
45 #define PLL_CON0_PLL_SHARED4 0x0280
46 #define PLL_CON3_PLL_SHARED4 0x028c
47 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
48 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
49 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
50 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1010
51 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS 0x1014
52 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1018
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x101c
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1020
55 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1024
56 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1028
57 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x102c
58 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
59 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1034
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS 0x1038
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x103c
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1040
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP 0x1044
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
65 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
66 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU 0x1050
67 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUS 0x1054
68 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM 0x1058
69 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x105c
70 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1060
71 #define CLK_CON_MUX_MUX_CLKCMU_DPU_ALT 0x1064
72 #define CLK_CON_MUX_MUX_CLKCMU_DSP_BUS 0x1068
73 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x106c
74 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1070
75 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1074
76 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1078
77 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x107c
78 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1080
79 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG 0x1084
80 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1088
81 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x108c
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x1090
83 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD 0x1094
84 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD 0x1098
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x109c
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a0
87 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10a4
88 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10a8
89 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS 0x10ac
90 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC 0x10b0
91 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU 0x10b4
92 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0 0x10b8
93 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD 0x10bc
94 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c0
95 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c4
96 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10c8
97 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10cc
98 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10d0
99 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10d4
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d8
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10dc
102 #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
103 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
104 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
105 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
106 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
107 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
108 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x180c
109 #define CLK_CON_DIV_CLKCMU_BUS1_SSS 0x1810
110 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1814
111 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1818
112 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x181c
113 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1820
114 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1824
115 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1828
116 #define CLK_CON_DIV_CLKCMU_CMU_BOOST 0x182c
117 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
118 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS 0x1834
119 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
120 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
121 #define CLK_CON_DIV_CLKCMU_CPUCL2_BUSP 0x1840
122 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1844
123 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1848
124 #define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU 0x184c
125 #define CLK_CON_DIV_CLKCMU_DNC_BUS 0x1850
126 #define CLK_CON_DIV_CLKCMU_DNC_BUSM 0x1854
127 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x1858
128 #define CLK_CON_DIV_CLKCMU_DSP_BUS 0x185c
129 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1860
130 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1864
131 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
132 #define CLK_CON_DIV_CLKCMU_HPM 0x186c
133 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1870
134 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1874
135 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1878
136 #define CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG 0x187c
137 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1880
138 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x1884
139 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1888
140 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD 0x188c
141 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD 0x1890
142 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1894
143 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x1898
144 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x189c
145 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18a0
146 #define CLK_CON_DIV_CLKCMU_MCSC_BUS 0x18a4
147 #define CLK_CON_DIV_CLKCMU_MCSC_GDC 0x18a8
148 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x18ac
149 #define CLK_CON_DIV_CLKCMU_MFC0_MFC0 0x18b0
150 #define CLK_CON_DIV_CLKCMU_MFC0_WFD 0x18b4
151 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18b8
152 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x18bc
153 #define CLK_CON_DIV_CLKCMU_OTP 0x18c0
154 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18c4
155 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c8
156 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18cc
157 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18d0
158 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18d4
159 #define CLK_CON_DIV_CLKCMU_SSP_BUS 0x18d8
160 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18dc
161 #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
162 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
163 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
164 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
165 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
166 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
167 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1900
168 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1904
169 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1908
170 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x190c
171 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x1910
172 #define CLK_CON_DIV_PLL_SHARED4_DIV3 0x1914
173 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x1918
174 #define CLK_CON_GAT_CLKCMU_G3D_BUS 0x2000
175 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2004
176 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
177 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x200c
178 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2010
179 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x2014
180 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS 0x2018
181 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x201c
182 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2020
183 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2024
184 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2028
185 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x202c
186 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2030
187 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2034
188 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x2038
189 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x203c
190 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2040
191 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP 0x2044
192 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2048
193 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x204c
194 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU 0x2050
195 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUS 0x2054
196 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM 0x2058
197 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x205c
198 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x2060
199 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2064
200 #define CLK_CON_GAT_GATE_CLKCMU_DSP_BUS 0x2068
201 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x206c
202 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2070
203 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2074
204 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x2078
205 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x207c
206 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x2080
207 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x2084
208 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG 0x2088
209 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x208c
210 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD 0x2090
211 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x2094
212 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD 0x2098
213 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD 0x209c
214 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20a0
215 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20a4
216 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20a8
217 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20ac
218 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS 0x20b0
219 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC 0x20b4
220 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0 0x20bc
221 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD 0x20c0
222 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c4
223 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c8
224 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20cc
225 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20d0
226 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d4
227 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d8
228 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20dc
229 #define CLK_CON_GAT_GATE_CLKCMU_SSP_BUS 0x20e0
230 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x20e4
231 #define CLK_CON_GAT_GATE_CLKCMU_VRA_BUS 0x20e8
678 * Replace PLL_CON{0,3}_PLL with CLK_MOUT_PLL and mout_pll
705 mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
707 mout_cmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 2),
709 mout_cmu_bus0_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
711 mout_cmu_bus1_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
713 mout_cmu_bus1_sss_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS, 0, 2),
715 mout_cmu_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
717 mout_cmu_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
719 mout_cmu_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
721 mout_cmu_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
723 mout_cmu_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1),
725 mout_cmu_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1),
727 mout_cmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
729 mout_cmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
732 0, 2),
735 0, 2),
738 0, 2),
741 0, 1),
744 0, 2),
746 mout_cmu_csis_bus_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
749 0, 1),
751 mout_cmu_dnc_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUS, 0, 2),
753 mout_cmu_dnc_busm_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM, 0, 2),
755 mout_cmu_dns_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
757 mout_cmu_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 1),
759 mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
761 mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
763 mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
765 mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1),
767 mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
769 mout_cmu_hsi0_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 1),
771 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
774 0, 2),
777 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2),
779 mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
782 0, 2),
784 mout_cmu_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
787 0, 2),
790 0, 1),
792 mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
794 mout_cmu_hsi2_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
796 mout_cmu_ipp_bus_p, CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
798 mout_cmu_itp_bus_p, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
800 mout_cmu_mcsc_bus_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, 0, 3),
802 mout_cmu_mcsc_gdc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, 0, 3),
805 0, 2),
807 mout_cmu_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 2),
809 mout_cmu_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 2),
811 mout_cmu_mif_busp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
813 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
815 mout_cmu_npu_bus_p, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
817 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
819 mout_cmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
821 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
823 mout_cmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
825 mout_cmu_peris_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
827 mout_cmu_ssp_bus_p, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, 0, 2),
829 mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
831 mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
837 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
839 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
841 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
845 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
847 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
849 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
853 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
857 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
859 CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
861 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
864 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
866 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
868 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
870 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
872 CLK_CON_DIV_CLKCMU_BUS1_SSS, 0, 4),
874 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
876 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
878 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
880 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
882 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
884 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
886 CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
888 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
891 0, 3),
893 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
895 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
897 "gout_cmu_cpucl2_busp", CLK_CON_DIV_CLKCMU_CPUCL2_BUSP, 0, 4),
899 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
901 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
903 "gout_cmu_csis_ois_mcu", CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, 0, 4),
905 CLK_CON_DIV_CLKCMU_DNC_BUS, 0, 4),
907 CLK_CON_DIV_CLKCMU_DNC_BUSM, 0, 4),
909 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
911 CLK_CON_DIV_CLKCMU_DSP_BUS, 0, 4),
913 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
915 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
917 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
919 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
921 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
923 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
925 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
928 0, 4),
930 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
933 0, 9),
935 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7),
938 0, 3),
941 0, 3),
943 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
945 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7),
947 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
949 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
951 CLK_CON_DIV_CLKCMU_MCSC_BUS, 0, 4),
953 CLK_CON_DIV_CLKCMU_MCSC_GDC, 0, 4),
956 0, 2),
958 CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0, 4),
960 CLK_CON_DIV_CLKCMU_MFC0_WFD, 0, 4),
962 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
964 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
966 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
968 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
970 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
972 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
974 CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
976 CLK_CON_DIV_CLKCMU_SSP_BUS, 0, 4),
978 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
980 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
982 CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4),
987 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
989 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
991 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, CLK_IGNORE_UNUSED, 0),
993 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, CLK_IGNORE_UNUSED, 0),
995 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS, 21, CLK_IGNORE_UNUSED, 0),
997 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
999 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1001 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1003 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1005 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1007 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1009 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IGNORE_UNUSED, 0),
1012 21, 0, 0),
1015 21, CLK_IGNORE_UNUSED, 0),
1018 21, CLK_IGNORE_UNUSED, 0),
1021 21, CLK_IGNORE_UNUSED, 0),
1024 21, CLK_IGNORE_UNUSED, 0),
1026 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1029 21, 0, 0),
1031 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS, 21, 0, 0),
1033 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM, 21, 0, 0),
1035 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1037 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
1039 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, CLK_IGNORE_UNUSED, 0),
1041 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 21, 0, 0),
1043 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1045 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1048 21, 0, 0),
1050 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1052 "mout_cmu_hsi0_bus", CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1055 21, 0, 0),
1058 21, 0, 0),
1061 21, 0, 0),
1063 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1066 21, 0, 0),
1069 21, 0, 0),
1072 21, 0, 0),
1075 21, 0, 0),
1077 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1080 21, 0, 0),
1082 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1084 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1086 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, 21, 0, 0),
1088 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, 21, 0, 0),
1091 21, 0, 0),
1093 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, 21, 0, 0),
1095 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1097 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
1100 21, 0, 0),
1103 21, 0, 0),
1106 21, 0, 0),
1109 21, 0, 0),
1112 21, CLK_IGNORE_UNUSED, 0),
1114 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS, 21, 0, 0),
1116 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1118 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS, 21, 0, 0),
1146 /* Register Offset definitions for CMU_HSI0 (0x10a00000) */
1147 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0600
1148 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0620
1149 #define PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER 0x0630
1150 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0610
1151 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x2004
1152 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK 0x2018
1153 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2014
1154 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2020
1155 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK 0x2044
1156 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2008
1157 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x200c
1158 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x2010
1159 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK 0x201c
1160 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2024
1161 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2028
1162 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x202c
1163 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2034
1164 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x203c
1165 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2040
1166 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2030
1167 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1168 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK 0x2048
1169 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x2038
1221 21, 0, 0),
1225 21, 0, 0),
1229 21, 0, 0),
1233 21, CLK_IS_CRITICAL, 0),
1237 21, 0, 0),
1241 21, 0, 0),
1245 21, 0, 0),
1249 21, CLK_IGNORE_UNUSED, 0),
1253 21, 0, 0),
1257 21, 0, 0),
1262 21, 0, 0),
1267 21, 0, 0),
1272 21, 0, 0),
1277 21, 0, 0),
1282 21, 0, 0),
1286 21, 0, 0),
1290 21, CLK_IGNORE_UNUSED, 0),
1294 21, CLK_IGNORE_UNUSED, 0),
1318 return 0; in exynos990_cmu_probe()