Lines Matching +full:cpu +full:- +full:interrupt +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <24000000>;
18 cpu-map {
21 cpu = <&cpu_0>;
24 cpu = <&cpu_1>;
27 cpu = <&cpu_2>;
30 cpu = <&cpu_3>;
36 cpu = <&cpu_4>;
39 cpu = <&cpu_5>;
42 cpu = <&cpu_6>;
45 cpu = <&cpu_7>;
50 cpu_0: cpu@0 {
52 device_type = "cpu";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
61 riscv,cbom-block-size = <64>;
62 riscv,cbop-block-size = <64>;
63 riscv,cboz-block-size = <64>;
64 i-cache-block-size = <64>;
65 i-cache-size = <32768>;
66 i-cache-sets = <128>;
67 d-cache-block-size = <64>;
68 d-cache-size = <32768>;
69 d-cache-sets = <128>;
70 next-level-cache = <&cluster0_l2_cache>;
71 mmu-type = "riscv,sv39";
73 cpu0_intc: interrupt-controller {
74 compatible = "riscv,cpu-intc";
75 interrupt-controller;
76 #interrupt-cells = <1>;
80 cpu_1: cpu@1 {
82 device_type = "cpu";
85 riscv,isa-base = "rv64i";
86 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
91 riscv,cbom-block-size = <64>;
92 riscv,cbop-block-size = <64>;
93 riscv,cboz-block-size = <64>;
94 i-cache-block-size = <64>;
95 i-cache-size = <32768>;
96 i-cache-sets = <128>;
97 d-cache-block-size = <64>;
98 d-cache-size = <32768>;
99 d-cache-sets = <128>;
100 next-level-cache = <&cluster0_l2_cache>;
101 mmu-type = "riscv,sv39";
103 cpu1_intc: interrupt-controller {
104 compatible = "riscv,cpu-intc";
105 interrupt-controller;
106 #interrupt-cells = <1>;
110 cpu_2: cpu@2 {
112 device_type = "cpu";
115 riscv,isa-base = "rv64i";
116 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
121 riscv,cbom-block-size = <64>;
122 riscv,cbop-block-size = <64>;
123 riscv,cboz-block-size = <64>;
124 i-cache-block-size = <64>;
125 i-cache-size = <32768>;
126 i-cache-sets = <128>;
127 d-cache-block-size = <64>;
128 d-cache-size = <32768>;
129 d-cache-sets = <128>;
130 next-level-cache = <&cluster0_l2_cache>;
131 mmu-type = "riscv,sv39";
133 cpu2_intc: interrupt-controller {
134 compatible = "riscv,cpu-intc";
135 interrupt-controller;
136 #interrupt-cells = <1>;
140 cpu_3: cpu@3 {
142 device_type = "cpu";
145 riscv,isa-base = "rv64i";
146 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
151 riscv,cbom-block-size = <64>;
152 riscv,cbop-block-size = <64>;
153 riscv,cboz-block-size = <64>;
154 i-cache-block-size = <64>;
155 i-cache-size = <32768>;
156 i-cache-sets = <128>;
157 d-cache-block-size = <64>;
158 d-cache-size = <32768>;
159 d-cache-sets = <128>;
160 next-level-cache = <&cluster0_l2_cache>;
161 mmu-type = "riscv,sv39";
163 cpu3_intc: interrupt-controller {
164 compatible = "riscv,cpu-intc";
165 interrupt-controller;
166 #interrupt-cells = <1>;
170 cpu_4: cpu@4 {
172 device_type = "cpu";
175 riscv,isa-base = "rv64i";
176 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
181 riscv,cbom-block-size = <64>;
182 riscv,cbop-block-size = <64>;
183 riscv,cboz-block-size = <64>;
184 i-cache-block-size = <64>;
185 i-cache-size = <32768>;
186 i-cache-sets = <128>;
187 d-cache-block-size = <64>;
188 d-cache-size = <32768>;
189 d-cache-sets = <128>;
190 next-level-cache = <&cluster1_l2_cache>;
191 mmu-type = "riscv,sv39";
193 cpu4_intc: interrupt-controller {
194 compatible = "riscv,cpu-intc";
195 interrupt-controller;
196 #interrupt-cells = <1>;
200 cpu_5: cpu@5 {
202 device_type = "cpu";
205 riscv,isa-base = "rv64i";
206 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
211 riscv,cbom-block-size = <64>;
212 riscv,cbop-block-size = <64>;
213 riscv,cboz-block-size = <64>;
214 i-cache-block-size = <64>;
215 i-cache-size = <32768>;
216 i-cache-sets = <128>;
217 d-cache-block-size = <64>;
218 d-cache-size = <32768>;
219 d-cache-sets = <128>;
220 next-level-cache = <&cluster1_l2_cache>;
221 mmu-type = "riscv,sv39";
223 cpu5_intc: interrupt-controller {
224 compatible = "riscv,cpu-intc";
225 interrupt-controller;
226 #interrupt-cells = <1>;
230 cpu_6: cpu@6 {
232 device_type = "cpu";
235 riscv,isa-base = "rv64i";
236 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
241 riscv,cbom-block-size = <64>;
242 riscv,cbop-block-size = <64>;
243 riscv,cboz-block-size = <64>;
244 i-cache-block-size = <64>;
245 i-cache-size = <32768>;
246 i-cache-sets = <128>;
247 d-cache-block-size = <64>;
248 d-cache-size = <32768>;
249 d-cache-sets = <128>;
250 next-level-cache = <&cluster1_l2_cache>;
251 mmu-type = "riscv,sv39";
253 cpu6_intc: interrupt-controller {
254 compatible = "riscv,cpu-intc";
255 interrupt-controller;
256 #interrupt-cells = <1>;
260 cpu_7: cpu@7 {
262 device_type = "cpu";
265 riscv,isa-base = "rv64i";
266 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
271 riscv,cbom-block-size = <64>;
272 riscv,cbop-block-size = <64>;
273 riscv,cboz-block-size = <64>;
274 i-cache-block-size = <64>;
275 i-cache-size = <32768>;
276 i-cache-sets = <128>;
277 d-cache-block-size = <64>;
278 d-cache-size = <32768>;
279 d-cache-sets = <128>;
280 next-level-cache = <&cluster1_l2_cache>;
281 mmu-type = "riscv,sv39";
283 cpu7_intc: interrupt-controller {
284 compatible = "riscv,cpu-intc";
285 interrupt-controller;
286 #interrupt-cells = <1>;
290 cluster0_l2_cache: l2-cache0 {
292 cache-block-size = <64>;
293 cache-level = <2>;
294 cache-size = <524288>;
295 cache-sets = <512>;
296 cache-unified;
299 cluster1_l2_cache: l2-cache1 {
301 cache-block-size = <64>;
302 cache-level = <2>;
303 cache-size = <524288>;
304 cache-sets = <512>;
305 cache-unified;
310 compatible = "simple-bus";
311 interrupt-parent = <&plic>;
312 #address-cells = <2>;
313 #size-cells = <2>;
314 dma-noncoherent;
318 compatible = "spacemit,k1-uart", "intel,xscale-uart";
321 clock-frequency = <14857000>;
322 reg-shift = <2>;
323 reg-io-width = <4>;
328 compatible = "spacemit,k1-uart", "intel,xscale-uart";
331 clock-frequency = <14857000>;
332 reg-shift = <2>;
333 reg-io-width = <4>;
338 compatible = "spacemit,k1-uart", "intel,xscale-uart";
341 clock-frequency = <14857000>;
342 reg-shift = <2>;
343 reg-io-width = <4>;
348 compatible = "spacemit,k1-uart", "intel,xscale-uart";
351 clock-frequency = <14857000>;
352 reg-shift = <2>;
353 reg-io-width = <4>;
358 compatible = "spacemit,k1-uart", "intel,xscale-uart";
361 clock-frequency = <14857000>;
362 reg-shift = <2>;
363 reg-io-width = <4>;
368 compatible = "spacemit,k1-uart", "intel,xscale-uart";
371 clock-frequency = <14857000>;
372 reg-shift = <2>;
373 reg-io-width = <4>;
378 compatible = "spacemit,k1-uart", "intel,xscale-uart";
381 clock-frequency = <14857000>;
382 reg-shift = <2>;
383 reg-io-width = <4>;
388 compatible = "spacemit,k1-uart", "intel,xscale-uart";
391 clock-frequency = <14857000>;
392 reg-shift = <2>;
393 reg-io-width = <4>;
398 compatible = "spacemit,k1-uart", "intel,xscale-uart";
401 clock-frequency = <14857000>;
402 reg-shift = <2>;
403 reg-io-width = <4>;
408 compatible = "spacemit,k1-pinctrl";
412 plic: interrupt-controller@e0000000 {
413 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
415 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
423 interrupt-controller;
424 #address-cells = <0>;
425 #interrupt-cells = <1>;
430 compatible = "spacemit,k1-clint", "sifive,clint0";
432 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
443 compatible = "spacemit,k1-uart", "intel,xscale-uart";
446 clock-frequency = <14857000>;
447 reg-shift = <2>;
448 reg-io-width = <4>;