Lines Matching full:aarch32
42 * For AArch32, we only take care of what is being trapped. Anything
474 * for both AArch64 and AArch32 accesses.
495 if (p->Op0 == 0) { /* AArch32 */
1210 /* The LC bit is RES1 when AArch32 is not supported */
1691 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
2624 /* AArch64 mappings of the AArch32 ID registers */
3139 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
3706 * AArch32 debug register mappings
3708 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
3709 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
4164 * backends between AArch32 and AArch64, we get away with it.
4195 * from AArch32.
4238 * VFP Register' from AArch32.
4265 * CRn=0, which corresponds to the AArch32 feature
4270 * Our cp15 system register tables do not enumerate the AArch32 feature
4271 * registers. Conveniently, our AArch64 table does, and the AArch32 system
4294 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
4345 * Certain AArch32 ID registers are handled by rerouting to the AArch64