Lines Matching +full:0 +full:xee000000
18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
71 #size-cells = <0>;
73 a53_0: cpu@0 {
75 reg = <0>;
97 L2_CA53: cache-controller-0 {
107 #clock-cells = <0>;
109 clock-frequency = <0>;
115 #clock-cells = <0>;
116 clock-frequency = <0>;
134 #clock-cells = <0>;
135 clock-frequency = <0>;
148 reg = <0 0xe6020000 0 0x0c>;
159 reg = <0 0xe6050000 0 0x50>;
163 gpio-ranges = <&pfc 0 0 18>;
174 reg = <0 0xe6051000 0 0x50>;
178 gpio-ranges = <&pfc 0 32 23>;
189 reg = <0 0xe6052000 0 0x50>;
193 gpio-ranges = <&pfc 0 64 26>;
204 reg = <0 0xe6053000 0 0x50>;
208 gpio-ranges = <&pfc 0 96 16>;
219 reg = <0 0xe6054000 0 0x50>;
223 gpio-ranges = <&pfc 0 128 11>;
234 reg = <0 0xe6055000 0 0x50>;
238 gpio-ranges = <&pfc 0 160 20>;
249 reg = <0 0xe6055400 0 0x50>;
253 gpio-ranges = <&pfc 0 192 18>;
263 reg = <0 0xe6060000 0 0x508>;
269 reg = <0 0xe60f0000 0 0x1004>;
282 reg = <0 0xe6130000 0 0x1004>;
301 reg = <0 0xe6140000 0 0x1004>;
320 reg = <0 0xe6148000 0 0x1004>;
338 reg = <0 0xe6150000 0 0x1000>;
342 #power-domain-cells = <0>;
348 reg = <0 0xe6160000 0 0x0200>;
353 reg = <0 0xe6180000 0 0x0400>;
359 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
366 #thermal-sensor-cells = <0>;
373 reg = <0 0xe61c0000 0 0x200>;
374 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
387 reg = <0 0xe61e0000 0 0x30>;
401 reg = <0 0xe6fc0000 0 0x30>;
416 reg = <0 0xe6fd0000 0 0x30>;
431 reg = <0 0xe6fe0000 0 0x30>;
445 reg = <0 0xffc00000 0 0x30>;
459 #size-cells = <0>;
462 reg = <0 0xe6500000 0 0x40>;
467 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
468 <&dmac2 0x91>, <&dmac2 0x90>;
476 #size-cells = <0>;
479 reg = <0 0xe6508000 0 0x40>;
484 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
485 <&dmac2 0x93>, <&dmac2 0x92>;
493 #size-cells = <0>;
496 reg = <0 0xe6510000 0 0x40>;
501 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
502 <&dmac2 0x95>, <&dmac2 0x94>;
510 #size-cells = <0>;
513 reg = <0 0xe66d0000 0 0x40>;
518 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
526 #size-cells = <0>;
529 reg = <0 0xe66d8000 0 0x40>;
534 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
542 #size-cells = <0>;
545 reg = <0 0xe66e0000 0 0x40>;
550 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
558 #size-cells = <0>;
561 reg = <0 0xe66e8000 0 0x40>;
566 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
574 #size-cells = <0>;
577 reg = <0 0xe6690000 0 0x40>;
588 #size-cells = <0>;
592 reg = <0 0xe60b0000 0 0x425>;
597 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
606 reg = <0 0xe6540000 0 0x60>;
612 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
613 <&dmac2 0x31>, <&dmac2 0x30>;
624 reg = <0 0xe6550000 0 0x60>;
630 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
631 <&dmac2 0x33>, <&dmac2 0x32>;
642 reg = <0 0xe6560000 0 0x60>;
648 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
649 <&dmac2 0x35>, <&dmac2 0x34>;
660 reg = <0 0xe66a0000 0 0x60>;
666 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
677 reg = <0 0xe66b0000 0 0x60>;
683 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
693 reg = <0 0xe6590000 0 0x200>;
696 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
697 <&usb_dmac1 0>, <&usb_dmac1 1>;
710 reg = <0 0xe65a0000 0 0x100>;
724 reg = <0 0xe65b0000 0 0x100>;
738 reg = <0 0xe6700000 0 0x10000>;
767 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
780 reg = <0 0xe7300000 0 0x10000>;
809 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
822 reg = <0 0xe7310000 0 0x10000>;
863 reg = <0 0xe6740000 0 0x1000>;
864 renesas,ipmmu-main = <&ipmmu_mm 0>;
871 reg = <0 0xe7740000 0 0x1000>;
879 reg = <0 0xe6570000 0 0x1000>;
887 reg = <0 0xe67b0000 0 0x1000>;
896 reg = <0 0xec670000 0 0x1000>;
904 reg = <0 0xfd800000 0 0x1000>;
912 reg = <0 0xfe6b0000 0 0x1000>;
920 reg = <0 0xfebd0000 0 0x1000>;
928 reg = <0 0xfe990000 0 0x1000>;
937 reg = <0 0xe6800000 0 0x800>;
975 rx-internal-delay-ps = <0>;
978 #size-cells = <0>;
985 reg = <0 0xe6c30000 0 0x1000>;
1001 reg = <0 0xe6c38000 0 0x1000>;
1017 reg = <0 0xe66c0000 0 0x8000>;
1042 reg = <0 0xe6e30000 0 0x8>;
1052 reg = <0 0xe6e31000 0 0x8>;
1062 reg = <0 0xe6e32000 0 0x8>;
1072 reg = <0 0xe6e33000 0 0x8>;
1082 reg = <0 0xe6e34000 0 0x8>;
1092 reg = <0 0xe6e35000 0 0x8>;
1102 reg = <0 0xe6e36000 0 0x8>;
1113 reg = <0 0xe6e60000 0 64>;
1119 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1120 <&dmac2 0x51>, <&dmac2 0x50>;
1130 reg = <0 0xe6e68000 0 64>;
1136 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1137 <&dmac2 0x53>, <&dmac2 0x52>;
1147 reg = <0 0xe6e88000 0 64>;
1153 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1154 <&dmac2 0x13>, <&dmac2 0x12>;
1164 reg = <0 0xe6c50000 0 64>;
1170 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1180 reg = <0 0xe6c40000 0 64>;
1186 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1196 reg = <0 0xe6f30000 0 64>;
1202 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1212 reg = <0 0xe6e90000 0 0x0064>;
1215 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1216 <&dmac2 0x41>, <&dmac2 0x40>;
1221 #size-cells = <0>;
1228 reg = <0 0xe6ea0000 0 0x0064>;
1231 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1236 #size-cells = <0>;
1243 reg = <0 0xe6c00000 0 0x0064>;
1246 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1251 #size-cells = <0>;
1258 reg = <0 0xe6c10000 0 0x0064>;
1261 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1266 #size-cells = <0>;
1272 reg = <0 0xe6ef4000 0 0x1000>;
1282 #size-cells = <0>;
1286 #size-cells = <0>;
1300 reg = <0 0xe6ef5000 0 0x1000>;
1310 #size-cells = <0>;
1314 #size-cells = <0>;
1330 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1336 * clkout : #clock-cells = <0>; <&rcar_sound>;
1341 reg = <0 0xec500000 0 0x1000>, /* SCU */
1342 <0 0xec5a0000 0 0x100>, /* ADG */
1343 <0 0xec540000 0 0x1000>, /* SSIU */
1344 <0 0xec541000 0 0x280>, /* SSI */
1345 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1368 "ssi.1", "ssi.0",
1371 "src.1", "src.0",
1372 "mix.1", "mix.0",
1373 "ctu.1", "ctu.0",
1374 "dvc.0", "dvc.1",
1386 "ssi.1", "ssi.0";
1390 ctu00: ctu-0 { };
1401 dvc0: dvc-0 {
1402 dmas = <&audma0 0xbc>;
1406 dmas = <&audma0 0xbe>;
1412 mix0: mix-0 { };
1417 src0: src-0 {
1419 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1424 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1429 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1434 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1439 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1444 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1449 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1454 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1459 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1464 dmas = <&audma0 0x97>, <&audma0 0xba>;
1470 ssi0: ssi-0 {
1472 dmas = <&audma0 0x01>, <&audma0 0x02>,
1473 <&audma0 0x15>, <&audma0 0x16>;
1478 dmas = <&audma0 0x03>, <&audma0 0x04>,
1479 <&audma0 0x49>, <&audma0 0x4a>;
1484 dmas = <&audma0 0x05>, <&audma0 0x06>,
1485 <&audma0 0x63>, <&audma0 0x64>;
1490 dmas = <&audma0 0x07>, <&audma0 0x08>,
1491 <&audma0 0x6f>, <&audma0 0x70>;
1496 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1497 <&audma0 0x71>, <&audma0 0x72>;
1502 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1503 <&audma0 0x73>, <&audma0 0x74>;
1508 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1509 <&audma0 0x75>, <&audma0 0x76>;
1514 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1515 <&audma0 0x79>, <&audma0 0x7a>;
1520 dmas = <&audma0 0x11>, <&audma0 0x12>,
1521 <&audma0 0x7b>, <&audma0 0x7c>;
1526 dmas = <&audma0 0x13>, <&audma0 0x14>,
1527 <&audma0 0x7d>, <&audma0 0x7e>;
1536 reg = <0 0xec700000 0 0x10000>;
1565 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1578 reg = <0 0xee000000 0 0xc00>;
1589 reg = <0 0xee020000 0 0x400>;
1599 reg = <0 0xee080000 0 0x100>;
1611 reg = <0 0xee080100 0 0x100>;
1625 reg = <0 0xee080200 0 0x700>;
1637 reg = <0 0xee100000 0 0x2000>;
1651 reg = <0 0xee120000 0 0x2000>;
1665 reg = <0 0xee160000 0 0x2000>;
1679 reg = <0 0xee200000 0 0x200>,
1680 <0 0x08000000 0 0x4000000>,
1681 <0 0xee208000 0 0x100>;
1688 #size-cells = <0>;
1695 #address-cells = <0>;
1697 reg = <0x0 0xf1010000 0 0x1000>,
1698 <0x0 0xf1020000 0 0x20000>,
1699 <0x0 0xf1040000 0 0x20000>,
1700 <0x0 0xf1060000 0 0x20000>;
1712 reg = <0 0xfe000000 0 0x80000>;
1715 bus-range = <0x00 0xff>;
1717 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1718 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1719 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1720 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1722 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1727 interrupt-map-mask = <0 0 0 0>;
1728 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1733 iommu-map = <0 &ipmmu_hc 0 1>;
1734 iommu-map-mask = <0>;
1741 reg = <0x0 0xfe000000 0 0x80000>,
1742 <0x0 0xfe100000 0 0x100000>,
1743 <0x0 0xfe200000 0 0x200000>,
1744 <0x0 0x30000000 0 0x8000000>,
1745 <0x0 0x38000000 0 0x8000000>;
1759 reg = <0 0xfe960000 0 0x8000>;
1769 reg = <0 0xfea20000 0 0x7000>;
1779 reg = <0 0xfea28000 0 0x7000>;
1789 reg = <0 0xfe9a0000 0 0x8000>;
1799 reg = <0 0xfe96f000 0 0x200>;
1808 reg = <0 0xfea27000 0 0x200>;
1817 reg = <0 0xfea2f000 0 0x200>;
1826 reg = <0 0xfe9af000 0 0x200>;
1835 reg = <0 0xfeaa0000 0 0x10000>;
1844 #size-cells = <0>;
1846 port@0 {
1847 reg = <0>;
1852 #size-cells = <0>;
1856 csi40vin4: endpoint@0 {
1857 reg = <0>;
1870 reg = <0 0xfeb00000 0 0x40000>;
1874 clock-names = "du.0", "du.1";
1876 reset-names = "du.0";
1877 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1883 #size-cells = <0>;
1885 port@0 {
1886 reg = <0>;
1907 reg = <0 0xfeb90000 0 0x20>;
1917 #size-cells = <0>;
1919 port@0 {
1920 reg = <0>;
1934 reg = <0 0xfeb90100 0 0x20>;
1942 #size-cells = <0>;
1944 port@0 {
1945 reg = <0>;
1959 reg = <0 0xfff00044 0 4>;
1966 polling-delay = <0>;
1973 cooling-device = <&a53_0 0 2>;
2006 #clock-cells = <0>;
2007 clock-frequency = <0>;
2012 #clock-cells = <0>;
2013 clock-frequency = <0>;