Lines Matching +full:- +full:cpg
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
40 /* External CAN clock - to be overridden by boards that provide it */
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-800000000 {
52 opp-hz = /bits/ 64 <800000000>;
53 opp-microvolt = <1030000>;
54 clock-latency-ns = <300000>;
56 opp-1000000000 {
57 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <1030000>;
59 clock-latency-ns = <300000>;
61 opp-1200000000 {
62 opp-hz = /bits/ 64 <1200000000>;
63 opp-microvolt = <1030000>;
64 clock-latency-ns = <300000>;
65 opp-suspend;
70 #address-cells = <1>;
71 #size-cells = <0>;
74 compatible = "arm,cortex-a53";
77 #cooling-cells = <2>;
78 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
79 next-level-cache = <&L2_CA53>;
80 enable-method = "psci";
81 dynamic-power-coefficient = <277>;
82 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
83 operating-points-v2 = <&cluster1_opp>;
87 compatible = "arm,cortex-a53";
90 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
91 next-level-cache = <&L2_CA53>;
92 enable-method = "psci";
93 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
94 operating-points-v2 = <&cluster1_opp>;
97 L2_CA53: cache-controller-0 {
99 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
100 cache-unified;
101 cache-level = <2>;
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
109 clock-frequency = <0>;
112 /* External PCIe clock - can be overridden by the board */
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <0>;
120 compatible = "arm,cortex-a53-pmu";
121 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
123 interrupt-affinity = <&a53_0>, <&a53_1>;
127 compatible = "arm,psci-1.0", "arm,psci-0.2";
131 /* External SCIF clock - to be overridden by boards that provide it */
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <0>;
139 compatible = "simple-bus";
140 interrupt-parent = <&gic>;
141 #address-cells = <2>;
142 #size-cells = <2>;
146 compatible = "renesas,r8a774c0-wdt",
147 "renesas,rcar-gen3-wdt";
150 clocks = <&cpg CPG_MOD 402>;
151 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
152 resets = <&cpg 402>;
157 compatible = "renesas,gpio-r8a774c0",
158 "renesas,rcar-gen3-gpio";
161 #gpio-cells = <2>;
162 gpio-controller;
163 gpio-ranges = <&pfc 0 0 18>;
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 clocks = <&cpg CPG_MOD 912>;
167 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
168 resets = <&cpg 912>;
172 compatible = "renesas,gpio-r8a774c0",
173 "renesas,rcar-gen3-gpio";
176 #gpio-cells = <2>;
177 gpio-controller;
178 gpio-ranges = <&pfc 0 32 23>;
179 #interrupt-cells = <2>;
180 interrupt-controller;
181 clocks = <&cpg CPG_MOD 911>;
182 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
183 resets = <&cpg 911>;
187 compatible = "renesas,gpio-r8a774c0",
188 "renesas,rcar-gen3-gpio";
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 64 26>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&cpg CPG_MOD 910>;
197 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
198 resets = <&cpg 910>;
202 compatible = "renesas,gpio-r8a774c0",
203 "renesas,rcar-gen3-gpio";
206 #gpio-cells = <2>;
207 gpio-controller;
208 gpio-ranges = <&pfc 0 96 16>;
209 #interrupt-cells = <2>;
210 interrupt-controller;
211 clocks = <&cpg CPG_MOD 909>;
212 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
213 resets = <&cpg 909>;
217 compatible = "renesas,gpio-r8a774c0",
218 "renesas,rcar-gen3-gpio";
221 #gpio-cells = <2>;
222 gpio-controller;
223 gpio-ranges = <&pfc 0 128 11>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 clocks = <&cpg CPG_MOD 908>;
227 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
228 resets = <&cpg 908>;
232 compatible = "renesas,gpio-r8a774c0",
233 "renesas,rcar-gen3-gpio";
236 #gpio-cells = <2>;
237 gpio-controller;
238 gpio-ranges = <&pfc 0 160 20>;
239 #interrupt-cells = <2>;
240 interrupt-controller;
241 clocks = <&cpg CPG_MOD 907>;
242 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
243 resets = <&cpg 907>;
247 compatible = "renesas,gpio-r8a774c0",
248 "renesas,rcar-gen3-gpio";
251 #gpio-cells = <2>;
252 gpio-controller;
253 gpio-ranges = <&pfc 0 192 18>;
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 clocks = <&cpg CPG_MOD 906>;
257 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
258 resets = <&cpg 906>;
262 compatible = "renesas,pfc-r8a774c0";
267 compatible = "renesas,r8a774c0-cmt0",
268 "renesas,rcar-gen3-cmt0";
272 clocks = <&cpg CPG_MOD 303>;
273 clock-names = "fck";
274 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
275 resets = <&cpg 303>;
280 compatible = "renesas,r8a774c0-cmt1",
281 "renesas,rcar-gen3-cmt1";
291 clocks = <&cpg CPG_MOD 302>;
292 clock-names = "fck";
293 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
294 resets = <&cpg 302>;
299 compatible = "renesas,r8a774c0-cmt1",
300 "renesas,rcar-gen3-cmt1";
310 clocks = <&cpg CPG_MOD 301>;
311 clock-names = "fck";
312 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
313 resets = <&cpg 301>;
318 compatible = "renesas,r8a774c0-cmt1",
319 "renesas,rcar-gen3-cmt1";
329 clocks = <&cpg CPG_MOD 300>;
330 clock-names = "fck";
331 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
332 resets = <&cpg 300>;
336 cpg: clock-controller@e6150000 { label
337 compatible = "renesas,r8a774c0-cpg-mssr";
340 clock-names = "extal";
341 #clock-cells = <2>;
342 #power-domain-cells = <0>;
343 #reset-cells = <1>;
346 rst: reset-controller@e6160000 {
347 compatible = "renesas,r8a774c0-rst";
351 sysc: system-controller@e6180000 {
352 compatible = "renesas,r8a774c0-sysc";
354 #power-domain-cells = <1>;
358 compatible = "renesas,thermal-r8a774c0";
363 clocks = <&cpg CPG_MOD 522>;
364 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
365 resets = <&cpg 522>;
366 #thermal-sensor-cells = <0>;
369 intc_ex: interrupt-controller@e61c0000 {
370 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
371 #interrupt-cells = <2>;
372 interrupt-controller;
380 clocks = <&cpg CPG_MOD 407>;
381 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
382 resets = <&cpg 407>;
386 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
391 interrupt-names = "tuni0", "tuni1", "tuni2";
392 clocks = <&cpg CPG_MOD 125>;
393 clock-names = "fck";
394 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
395 resets = <&cpg 125>;
400 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
406 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
407 clocks = <&cpg CPG_MOD 124>;
408 clock-names = "fck";
409 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
410 resets = <&cpg 124>;
415 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
421 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
422 clocks = <&cpg CPG_MOD 123>;
423 clock-names = "fck";
424 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
425 resets = <&cpg 123>;
430 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
435 interrupt-names = "tuni0", "tuni1", "tuni2";
436 clocks = <&cpg CPG_MOD 122>;
437 clock-names = "fck";
438 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
439 resets = <&cpg 122>;
444 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
449 interrupt-names = "tuni0", "tuni1", "tuni2";
450 clocks = <&cpg CPG_MOD 121>;
451 clock-names = "fck";
452 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
453 resets = <&cpg 121>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460 compatible = "renesas,i2c-r8a774c0",
461 "renesas,rcar-gen3-i2c";
464 clocks = <&cpg CPG_MOD 931>;
465 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
466 resets = <&cpg 931>;
469 dma-names = "tx", "rx", "tx", "rx";
470 i2c-scl-internal-delay-ns = <110>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 compatible = "renesas,i2c-r8a774c0",
478 "renesas,rcar-gen3-i2c";
481 clocks = <&cpg CPG_MOD 930>;
482 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
483 resets = <&cpg 930>;
486 dma-names = "tx", "rx", "tx", "rx";
487 i2c-scl-internal-delay-ns = <6>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "renesas,i2c-r8a774c0",
495 "renesas,rcar-gen3-i2c";
498 clocks = <&cpg CPG_MOD 929>;
499 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
500 resets = <&cpg 929>;
503 dma-names = "tx", "rx", "tx", "rx";
504 i2c-scl-internal-delay-ns = <6>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "renesas,i2c-r8a774c0",
512 "renesas,rcar-gen3-i2c";
515 clocks = <&cpg CPG_MOD 928>;
516 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
517 resets = <&cpg 928>;
519 dma-names = "tx", "rx";
520 i2c-scl-internal-delay-ns = <110>;
525 #address-cells = <1>;
526 #size-cells = <0>;
527 compatible = "renesas,i2c-r8a774c0",
528 "renesas,rcar-gen3-i2c";
531 clocks = <&cpg CPG_MOD 927>;
532 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
533 resets = <&cpg 927>;
535 dma-names = "tx", "rx";
536 i2c-scl-internal-delay-ns = <6>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "renesas,i2c-r8a774c0",
544 "renesas,rcar-gen3-i2c";
547 clocks = <&cpg CPG_MOD 919>;
548 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
549 resets = <&cpg 919>;
551 dma-names = "tx", "rx";
552 i2c-scl-internal-delay-ns = <6>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "renesas,i2c-r8a774c0",
560 "renesas,rcar-gen3-i2c";
563 clocks = <&cpg CPG_MOD 918>;
564 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
565 resets = <&cpg 918>;
567 dma-names = "tx", "rx";
568 i2c-scl-internal-delay-ns = <6>;
573 #address-cells = <1>;
574 #size-cells = <0>;
575 compatible = "renesas,i2c-r8a774c0",
576 "renesas,rcar-gen3-i2c";
579 clocks = <&cpg CPG_MOD 1003>;
580 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
581 resets = <&cpg 1003>;
582 i2c-scl-internal-delay-ns = <6>;
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "renesas,iic-r8a774c0",
590 "renesas,rcar-gen3-iic",
591 "renesas,rmobile-iic";
594 clocks = <&cpg CPG_MOD 926>;
595 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
596 resets = <&cpg 926>;
598 dma-names = "tx", "rx";
603 compatible = "renesas,hscif-r8a774c0",
604 "renesas,rcar-gen3-hscif",
608 clocks = <&cpg CPG_MOD 520>,
609 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
611 clock-names = "fck", "brg_int", "scif_clk";
614 dma-names = "tx", "rx", "tx", "rx";
615 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
616 resets = <&cpg 520>;
621 compatible = "renesas,hscif-r8a774c0",
622 "renesas,rcar-gen3-hscif",
626 clocks = <&cpg CPG_MOD 519>,
627 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
629 clock-names = "fck", "brg_int", "scif_clk";
632 dma-names = "tx", "rx", "tx", "rx";
633 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
634 resets = <&cpg 519>;
639 compatible = "renesas,hscif-r8a774c0",
640 "renesas,rcar-gen3-hscif",
644 clocks = <&cpg CPG_MOD 518>,
645 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
647 clock-names = "fck", "brg_int", "scif_clk";
650 dma-names = "tx", "rx", "tx", "rx";
651 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
652 resets = <&cpg 518>;
657 compatible = "renesas,hscif-r8a774c0",
658 "renesas,rcar-gen3-hscif",
662 clocks = <&cpg CPG_MOD 517>,
663 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
665 clock-names = "fck", "brg_int", "scif_clk";
667 dma-names = "tx", "rx";
668 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
669 resets = <&cpg 517>;
674 compatible = "renesas,hscif-r8a774c0",
675 "renesas,rcar-gen3-hscif",
679 clocks = <&cpg CPG_MOD 516>,
680 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
682 clock-names = "fck", "brg_int", "scif_clk";
684 dma-names = "tx", "rx";
685 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
686 resets = <&cpg 516>;
691 compatible = "renesas,usbhs-r8a774c0",
692 "renesas,rcar-gen3-usbhs";
695 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
698 dma-names = "ch0", "ch1", "ch2", "ch3";
701 phy-names = "usb";
702 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
703 resets = <&cpg 704>, <&cpg 703>;
707 usb_dmac0: dma-controller@e65a0000 {
708 compatible = "renesas,r8a774c0-usb-dmac",
709 "renesas,usb-dmac";
713 interrupt-names = "ch0", "ch1";
714 clocks = <&cpg CPG_MOD 330>;
715 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
716 resets = <&cpg 330>;
717 #dma-cells = <1>;
718 dma-channels = <2>;
721 usb_dmac1: dma-controller@e65b0000 {
722 compatible = "renesas,r8a774c0-usb-dmac",
723 "renesas,usb-dmac";
727 interrupt-names = "ch0", "ch1";
728 clocks = <&cpg CPG_MOD 331>;
729 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
730 resets = <&cpg 331>;
731 #dma-cells = <1>;
732 dma-channels = <2>;
735 dmac0: dma-controller@e6700000 {
736 compatible = "renesas,dmac-r8a774c0",
737 "renesas,rcar-dmac";
756 interrupt-names = "error",
761 clocks = <&cpg CPG_MOD 219>;
762 clock-names = "fck";
763 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
764 resets = <&cpg 219>;
765 #dma-cells = <1>;
766 dma-channels = <16>;
777 dmac1: dma-controller@e7300000 {
778 compatible = "renesas,dmac-r8a774c0",
779 "renesas,rcar-dmac";
798 interrupt-names = "error",
803 clocks = <&cpg CPG_MOD 218>;
804 clock-names = "fck";
805 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
806 resets = <&cpg 218>;
807 #dma-cells = <1>;
808 dma-channels = <16>;
819 dmac2: dma-controller@e7310000 {
820 compatible = "renesas,dmac-r8a774c0",
821 "renesas,rcar-dmac";
840 interrupt-names = "error",
845 clocks = <&cpg CPG_MOD 217>;
846 clock-names = "fck";
847 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
848 resets = <&cpg 217>;
849 #dma-cells = <1>;
850 dma-channels = <16>;
862 compatible = "renesas,ipmmu-r8a774c0";
864 renesas,ipmmu-main = <&ipmmu_mm 0>;
865 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
866 #iommu-cells = <1>;
870 compatible = "renesas,ipmmu-r8a774c0";
872 renesas,ipmmu-main = <&ipmmu_mm 1>;
873 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
874 #iommu-cells = <1>;
878 compatible = "renesas,ipmmu-r8a774c0";
880 renesas,ipmmu-main = <&ipmmu_mm 2>;
881 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
882 #iommu-cells = <1>;
886 compatible = "renesas,ipmmu-r8a774c0";
890 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
891 #iommu-cells = <1>;
895 compatible = "renesas,ipmmu-r8a774c0";
897 renesas,ipmmu-main = <&ipmmu_mm 4>;
898 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
899 #iommu-cells = <1>;
903 compatible = "renesas,ipmmu-r8a774c0";
905 renesas,ipmmu-main = <&ipmmu_mm 6>;
906 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
907 #iommu-cells = <1>;
911 compatible = "renesas,ipmmu-r8a774c0";
913 renesas,ipmmu-main = <&ipmmu_mm 12>;
914 power-domains = <&sysc R8A774C0_PD_A3VC>;
915 #iommu-cells = <1>;
919 compatible = "renesas,ipmmu-r8a774c0";
921 renesas,ipmmu-main = <&ipmmu_mm 14>;
922 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
923 #iommu-cells = <1>;
927 compatible = "renesas,ipmmu-r8a774c0";
929 renesas,ipmmu-main = <&ipmmu_mm 16>;
930 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
931 #iommu-cells = <1>;
935 compatible = "renesas,etheravb-r8a774c0",
936 "renesas,etheravb-rcar-gen3";
963 interrupt-names = "ch0", "ch1", "ch2", "ch3",
970 clocks = <&cpg CPG_MOD 812>;
971 clock-names = "fck";
972 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
973 resets = <&cpg 812>;
974 phy-mode = "rgmii";
975 rx-internal-delay-ps = <0>;
977 #address-cells = <1>;
978 #size-cells = <0>;
983 compatible = "renesas,can-r8a774c0",
984 "renesas,rcar-gen3-can";
987 clocks = <&cpg CPG_MOD 916>,
988 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
990 clock-names = "clkp1", "clkp2", "can_clk";
991 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
992 assigned-clock-rates = <40000000>;
993 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
994 resets = <&cpg 916>;
999 compatible = "renesas,can-r8a774c0",
1000 "renesas,rcar-gen3-can";
1003 clocks = <&cpg CPG_MOD 915>,
1004 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1006 clock-names = "clkp1", "clkp2", "can_clk";
1007 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1008 assigned-clock-rates = <40000000>;
1009 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1010 resets = <&cpg 915>;
1015 compatible = "renesas,r8a774c0-canfd",
1016 "renesas,rcar-gen3-canfd";
1020 interrupt-names = "ch_int", "g_int";
1021 clocks = <&cpg CPG_MOD 914>,
1022 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1024 clock-names = "fck", "canfd", "can_clk";
1025 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1026 assigned-clock-rates = <40000000>;
1027 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1028 resets = <&cpg 914>;
1041 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1043 clocks = <&cpg CPG_MOD 523>;
1044 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1045 resets = <&cpg 523>;
1046 #pwm-cells = <2>;
1051 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1053 clocks = <&cpg CPG_MOD 523>;
1054 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1055 resets = <&cpg 523>;
1056 #pwm-cells = <2>;
1061 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1063 clocks = <&cpg CPG_MOD 523>;
1064 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1065 resets = <&cpg 523>;
1066 #pwm-cells = <2>;
1071 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1073 clocks = <&cpg CPG_MOD 523>;
1074 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1075 resets = <&cpg 523>;
1076 #pwm-cells = <2>;
1081 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1083 clocks = <&cpg CPG_MOD 523>;
1084 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1085 resets = <&cpg 523>;
1086 #pwm-cells = <2>;
1091 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1093 clocks = <&cpg CPG_MOD 523>;
1094 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1095 resets = <&cpg 523>;
1096 #pwm-cells = <2>;
1101 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1103 clocks = <&cpg CPG_MOD 523>;
1104 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1105 resets = <&cpg 523>;
1106 #pwm-cells = <2>;
1111 compatible = "renesas,scif-r8a774c0",
1112 "renesas,rcar-gen3-scif", "renesas,scif";
1115 clocks = <&cpg CPG_MOD 207>,
1116 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1118 clock-names = "fck", "brg_int", "scif_clk";
1121 dma-names = "tx", "rx", "tx", "rx";
1122 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1123 resets = <&cpg 207>;
1128 compatible = "renesas,scif-r8a774c0",
1129 "renesas,rcar-gen3-scif", "renesas,scif";
1132 clocks = <&cpg CPG_MOD 206>,
1133 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1135 clock-names = "fck", "brg_int", "scif_clk";
1138 dma-names = "tx", "rx", "tx", "rx";
1139 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1140 resets = <&cpg 206>;
1145 compatible = "renesas,scif-r8a774c0",
1146 "renesas,rcar-gen3-scif", "renesas,scif";
1149 clocks = <&cpg CPG_MOD 310>,
1150 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1152 clock-names = "fck", "brg_int", "scif_clk";
1155 dma-names = "tx", "rx", "tx", "rx";
1156 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1157 resets = <&cpg 310>;
1162 compatible = "renesas,scif-r8a774c0",
1163 "renesas,rcar-gen3-scif", "renesas,scif";
1166 clocks = <&cpg CPG_MOD 204>,
1167 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1169 clock-names = "fck", "brg_int", "scif_clk";
1171 dma-names = "tx", "rx";
1172 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1173 resets = <&cpg 204>;
1178 compatible = "renesas,scif-r8a774c0",
1179 "renesas,rcar-gen3-scif", "renesas,scif";
1182 clocks = <&cpg CPG_MOD 203>,
1183 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1185 clock-names = "fck", "brg_int", "scif_clk";
1187 dma-names = "tx", "rx";
1188 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1189 resets = <&cpg 203>;
1194 compatible = "renesas,scif-r8a774c0",
1195 "renesas,rcar-gen3-scif", "renesas,scif";
1198 clocks = <&cpg CPG_MOD 202>,
1199 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1201 clock-names = "fck", "brg_int", "scif_clk";
1203 dma-names = "tx", "rx";
1204 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1205 resets = <&cpg 202>;
1210 compatible = "renesas,msiof-r8a774c0",
1211 "renesas,rcar-gen3-msiof";
1214 clocks = <&cpg CPG_MOD 211>;
1217 dma-names = "tx", "rx", "tx", "rx";
1218 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1219 resets = <&cpg 211>;
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1226 compatible = "renesas,msiof-r8a774c0",
1227 "renesas,rcar-gen3-msiof";
1230 clocks = <&cpg CPG_MOD 210>;
1232 dma-names = "tx", "rx";
1233 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1234 resets = <&cpg 210>;
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1241 compatible = "renesas,msiof-r8a774c0",
1242 "renesas,rcar-gen3-msiof";
1245 clocks = <&cpg CPG_MOD 209>;
1247 dma-names = "tx", "rx";
1248 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1249 resets = <&cpg 209>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1256 compatible = "renesas,msiof-r8a774c0",
1257 "renesas,rcar-gen3-msiof";
1260 clocks = <&cpg CPG_MOD 208>;
1262 dma-names = "tx", "rx";
1263 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1264 resets = <&cpg 208>;
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1271 compatible = "renesas,vin-r8a774c0";
1274 clocks = <&cpg CPG_MOD 807>;
1275 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1276 resets = <&cpg 807>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1292 remote-endpoint = <&csi40vin4>;
1299 compatible = "renesas,vin-r8a774c0";
1302 clocks = <&cpg CPG_MOD 806>;
1303 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1304 resets = <&cpg 806>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1320 remote-endpoint = <&csi40vin5>;
1328 * #sound-dai-cells is required if simple-card
1330 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1331 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1334 * #clock-cells is required for audio_clkout0/1/2/3
1336 * clkout : #clock-cells = <0>; <&rcar_sound>;
1337 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1339 compatible = "renesas,rcar_sound-r8a774c0",
1340 "renesas,rcar_sound-gen3";
1346 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1348 clocks = <&cpg CPG_MOD 1005>,
1349 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1350 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1351 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1352 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1353 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1354 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1355 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1356 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1357 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1358 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1359 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1360 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1361 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1364 <&cpg CPG_MOD 922>;
1365 clock-names = "ssi-all",
1376 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1377 resets = <&cpg 1005>,
1378 <&cpg 1006>, <&cpg 1007>,
1379 <&cpg 1008>, <&cpg 1009>,
1380 <&cpg 1010>, <&cpg 1011>,
1381 <&cpg 1012>, <&cpg 1013>,
1382 <&cpg 1014>, <&cpg 1015>;
1383 reset-names = "ssi-all",
1390 ctu00: ctu-0 { };
1391 ctu01: ctu-1 { };
1392 ctu02: ctu-2 { };
1393 ctu03: ctu-3 { };
1394 ctu10: ctu-4 { };
1395 ctu11: ctu-5 { };
1396 ctu12: ctu-6 { };
1397 ctu13: ctu-7 { };
1401 dvc0: dvc-0 {
1403 dma-names = "tx";
1405 dvc1: dvc-1 {
1407 dma-names = "tx";
1412 mix0: mix-0 { };
1413 mix1: mix-1 { };
1417 src0: src-0 {
1420 dma-names = "rx", "tx";
1422 src1: src-1 {
1425 dma-names = "rx", "tx";
1427 src2: src-2 {
1430 dma-names = "rx", "tx";
1432 src3: src-3 {
1435 dma-names = "rx", "tx";
1437 src4: src-4 {
1440 dma-names = "rx", "tx";
1442 src5: src-5 {
1445 dma-names = "rx", "tx";
1447 src6: src-6 {
1450 dma-names = "rx", "tx";
1452 src7: src-7 {
1455 dma-names = "rx", "tx";
1457 src8: src-8 {
1460 dma-names = "rx", "tx";
1462 src9: src-9 {
1465 dma-names = "rx", "tx";
1470 ssi0: ssi-0 {
1474 dma-names = "rx", "tx", "rxu", "txu";
1476 ssi1: ssi-1 {
1480 dma-names = "rx", "tx", "rxu", "txu";
1482 ssi2: ssi-2 {
1486 dma-names = "rx", "tx", "rxu", "txu";
1488 ssi3: ssi-3 {
1492 dma-names = "rx", "tx", "rxu", "txu";
1494 ssi4: ssi-4 {
1498 dma-names = "rx", "tx", "rxu", "txu";
1500 ssi5: ssi-5 {
1504 dma-names = "rx", "tx", "rxu", "txu";
1506 ssi6: ssi-6 {
1510 dma-names = "rx", "tx", "rxu", "txu";
1512 ssi7: ssi-7 {
1516 dma-names = "rx", "tx", "rxu", "txu";
1518 ssi8: ssi-8 {
1522 dma-names = "rx", "tx", "rxu", "txu";
1524 ssi9: ssi-9 {
1528 dma-names = "rx", "tx", "rxu", "txu";
1533 audma0: dma-controller@ec700000 {
1534 compatible = "renesas,dmac-r8a774c0",
1535 "renesas,rcar-dmac";
1554 interrupt-names = "error",
1559 clocks = <&cpg CPG_MOD 502>;
1560 clock-names = "fck";
1561 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1562 resets = <&cpg 502>;
1563 #dma-cells = <1>;
1564 dma-channels = <16>;
1576 compatible = "renesas,xhci-r8a774c0",
1577 "renesas,rcar-gen3-xhci";
1580 clocks = <&cpg CPG_MOD 328>;
1581 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1582 resets = <&cpg 328>;
1587 compatible = "renesas,r8a774c0-usb3-peri",
1588 "renesas,rcar-gen3-usb3-peri";
1591 clocks = <&cpg CPG_MOD 328>;
1592 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1593 resets = <&cpg 328>;
1598 compatible = "generic-ohci";
1601 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1603 phy-names = "usb";
1604 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1605 resets = <&cpg 703>, <&cpg 704>;
1610 compatible = "generic-ehci";
1613 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1615 phy-names = "usb";
1617 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1618 resets = <&cpg 703>, <&cpg 704>;
1622 usb2_phy0: usb-phy@ee080200 {
1623 compatible = "renesas,usb2-phy-r8a774c0",
1624 "renesas,rcar-gen3-usb2-phy";
1627 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1628 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1629 resets = <&cpg 703>, <&cpg 704>;
1630 #phy-cells = <1>;
1635 compatible = "renesas,sdhi-r8a774c0",
1636 "renesas,rcar-gen3-sdhi";
1639 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
1640 clock-names = "core", "clkh";
1641 max-frequency = <200000000>;
1642 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1643 resets = <&cpg 314>;
1649 compatible = "renesas,sdhi-r8a774c0",
1650 "renesas,rcar-gen3-sdhi";
1653 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
1654 clock-names = "core", "clkh";
1655 max-frequency = <200000000>;
1656 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1657 resets = <&cpg 313>;
1663 compatible = "renesas,sdhi-r8a774c0",
1664 "renesas,rcar-gen3-sdhi";
1667 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
1668 clock-names = "core", "clkh";
1669 max-frequency = <200000000>;
1670 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1671 resets = <&cpg 311>;
1677 compatible = "renesas,r8a774c0-rpc-if",
1678 "renesas,rcar-gen3-rpc-if";
1682 reg-names = "regs", "dirmap", "wbuf";
1684 clocks = <&cpg CPG_MOD 917>;
1685 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1686 resets = <&cpg 917>;
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1692 gic: interrupt-controller@f1010000 {
1693 compatible = "arm,gic-400";
1694 #interrupt-cells = <3>;
1695 #address-cells = <0>;
1696 interrupt-controller;
1703 clocks = <&cpg CPG_MOD 408>;
1704 clock-names = "clk";
1705 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1706 resets = <&cpg 408>;
1710 compatible = "renesas,pcie-r8a774c0",
1711 "renesas,pcie-rcar-gen3";
1713 #address-cells = <3>;
1714 #size-cells = <2>;
1715 bus-range = <0x00 0xff>;
1722 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1726 #interrupt-cells = <1>;
1727 interrupt-map-mask = <0 0 0 0>;
1728 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1729 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1730 clock-names = "pcie", "pcie_bus";
1731 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1732 resets = <&cpg 319>;
1733 iommu-map = <0 &ipmmu_hc 0 1>;
1734 iommu-map-mask = <0>;
1738 pciec0_ep: pcie-ep@fe000000 {
1739 compatible = "renesas,r8a774c0-pcie-ep",
1740 "renesas,rcar-gen3-pcie-ep";
1746 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1750 clocks = <&cpg CPG_MOD 319>;
1751 clock-names = "pcie";
1752 resets = <&cpg 319>;
1753 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1761 clocks = <&cpg CPG_MOD 626>;
1762 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1763 resets = <&cpg 626>;
1771 clocks = <&cpg CPG_MOD 623>;
1772 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1773 resets = <&cpg 623>;
1781 clocks = <&cpg CPG_MOD 622>;
1782 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1783 resets = <&cpg 622>;
1791 clocks = <&cpg CPG_MOD 631>;
1792 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1793 resets = <&cpg 631>;
1800 clocks = <&cpg CPG_MOD 607>;
1801 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1802 resets = <&cpg 607>;
1809 clocks = <&cpg CPG_MOD 603>;
1810 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1811 resets = <&cpg 603>;
1818 clocks = <&cpg CPG_MOD 602>;
1819 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1820 resets = <&cpg 602>;
1827 clocks = <&cpg CPG_MOD 611>;
1828 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1829 resets = <&cpg 611>;
1834 compatible = "renesas,r8a774c0-csi2";
1837 clocks = <&cpg CPG_MOD 716>;
1838 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1839 resets = <&cpg 716>;
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1851 #address-cells = <1>;
1852 #size-cells = <0>;
1858 remote-endpoint = <&vin4csi40>;
1862 remote-endpoint = <&vin5csi40>;
1869 compatible = "renesas,du-r8a774c0";
1873 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1874 clock-names = "du.0", "du.1";
1875 resets = <&cpg 724>;
1876 reset-names = "du.0";
1882 #address-cells = <1>;
1883 #size-cells = <0>;
1892 remote-endpoint = <&lvds0_in>;
1899 remote-endpoint = <&lvds1_in>;
1905 lvds0: lvds-encoder@feb90000 {
1906 compatible = "renesas,r8a774c0-lvds";
1908 clocks = <&cpg CPG_MOD 727>;
1909 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1910 resets = <&cpg 727>;
1916 #address-cells = <1>;
1917 #size-cells = <0>;
1922 remote-endpoint = <&du_out_lvds0>;
1932 lvds1: lvds-encoder@feb90100 {
1933 compatible = "renesas,r8a774c0-lvds";
1935 clocks = <&cpg CPG_MOD 727>;
1936 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1937 resets = <&cpg 726>;
1941 #address-cells = <1>;
1942 #size-cells = <0>;
1947 remote-endpoint = <&du_out_lvds1>;
1963 thermal-zones {
1964 cpu-thermal {
1965 polling-delay-passive = <250>;
1966 polling-delay = <0>;
1967 thermal-sensors = <&thermal>;
1968 sustainable-power = <717>;
1970 cooling-maps {
1973 cooling-device = <&a53_0 0 2>;
1979 sensor1_crit: sensor1-crit {
1985 target: trip-point1 {
1995 compatible = "arm,armv8-timer";
1996 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2000 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
2003 /* External USB clocks - can be overridden by the board */
2005 compatible = "fixed-clock";
2006 #clock-cells = <0>;
2007 clock-frequency = <0>;
2011 compatible = "fixed-clock";
2012 #clock-cells = <0>;
2013 clock-frequency = <0>;