Lines Matching +full:spi +full:- +full:qup +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
8 #include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
9 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/soc/qcom,gpr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/thermal/thermal.h>
23 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <19200000>;
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <32764>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a55";
53 enable-method = "psci";
54 next-level-cache = <&l2_0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
58 #cooling-cells = <2>;
60 l2_0: l2-cache {
62 cache-level = <2>;
63 cache-unified;
64 next-level-cache = <&l3_0>;
66 l3_0: l3-cache {
68 cache-level = <3>;
69 cache-unified;
76 compatible = "arm,cortex-a55";
79 enable-method = "psci";
80 next-level-cache = <&l2_100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
82 power-domains = <&cpu_pd1>;
83 power-domain-names = "psci";
84 #cooling-cells = <2>;
86 l2_100: l2-cache {
88 cache-level = <2>;
89 cache-unified;
90 next-level-cache = <&l3_0>;
96 compatible = "arm,cortex-a55";
99 enable-method = "psci";
100 next-level-cache = <&l2_200>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 power-domains = <&cpu_pd2>;
103 power-domain-names = "psci";
104 #cooling-cells = <2>;
106 l2_200: l2-cache {
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&l3_0>;
116 compatible = "arm,cortex-a55";
119 enable-method = "psci";
120 next-level-cache = <&l2_300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 power-domains = <&cpu_pd3>;
123 power-domain-names = "psci";
124 #cooling-cells = <2>;
126 l2_300: l2-cache {
128 cache-level = <2>;
129 cache-unified;
130 next-level-cache = <&l3_0>;
134 cpu-map {
154 idle-states {
155 entry-method = "psci";
157 cpu_sleep_0: cpu-sleep-0-0 {
158 compatible = "arm,idle-state";
159 idle-state-name = "silver-power-collapse";
160 arm,psci-suspend-param = <0x40000003>;
161 entry-latency-us = <549>;
162 exit-latency-us = <901>;
163 min-residency-us = <1774>;
164 local-timer-stop;
167 cpu_sleep_1: cpu-sleep-0-1 {
168 compatible = "arm,idle-state";
169 idle-state-name = "silver-rail-power-collapse";
170 arm,psci-suspend-param = <0x40000004>;
171 entry-latency-us = <702>;
172 exit-latency-us = <915>;
173 min-residency-us = <4001>;
174 local-timer-stop;
178 domain-idle-states {
179 cluster_sleep_0: cluster-sleep-0 {
180 compatible = "domain-idle-state";
181 arm,psci-suspend-param = <0x41000044>;
182 entry-latency-us = <2752>;
183 exit-latency-us = <3048>;
184 min-residency-us = <6118>;
187 cluster_sleep_1: cluster-sleep-1 {
188 compatible = "domain-idle-state";
189 arm,psci-suspend-param = <0x41002344>;
190 entry-latency-us = <3263>;
191 exit-latency-us = <4562>;
192 min-residency-us = <8467>;
195 cluster_sleep_2: cluster-sleep-2 {
196 compatible = "domain-idle-state";
197 arm,psci-suspend-param = <0x4100c344>;
198 entry-latency-us = <3638>;
199 exit-latency-us = <6562>;
200 min-residency-us = <9862>;
207 compatible = "qcom,scm-sar2130p", "qcom,scm";
208 qcom,dload-mode = <&tcsr_mutex 0x13000>;
214 clk_virt: interconnect-0 {
215 compatible = "qcom,sar2130p-clk-virt";
216 #interconnect-cells = <2>;
217 qcom,bcm-voters = <&apps_bcm_voter>;
220 mc_virt: interconnect-1 {
221 compatible = "qcom,sar2130p-mc-virt";
222 #interconnect-cells = <2>;
223 qcom,bcm-voters = <&apps_bcm_voter>;
233 compatible = "arm,armv8-pmuv3";
238 compatible = "arm,psci-1.0";
241 cpu_pd0: power-domain-cpu0 {
242 #power-domain-cells = <0>;
243 power-domains = <&cluster_pd>;
244 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
247 cpu_pd1: power-domain-cpu1 {
248 #power-domain-cells = <0>;
249 power-domains = <&cluster_pd>;
250 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
253 cpu_pd2: power-domain-cpu2 {
254 #power-domain-cells = <0>;
255 power-domains = <&cluster_pd>;
256 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
259 cpu_pd3: power-domain-cpu3 {
260 #power-domain-cells = <0>;
261 power-domains = <&cluster_pd>;
262 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
265 cluster_pd: power-domain-cpu-cluster0 {
266 #power-domain-cells = <0>;
267 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>;
271 reserved_memory: reserved-memory {
272 #address-cells = <2>;
273 #size-cells = <2>;
278 no-map;
281 xbl_dt_log_mem: xbl-dt-log@80600000 {
283 no-map;
286 xbl_ramdump_mem: xbl-ramdump@80640000 {
288 no-map;
291 aop_image_mem: aop-image@80800000 {
293 no-map;
296 aop_cmd_db_mem: aop-cmd-db@80860000 {
297 compatible = "qcom,cmd-db";
299 no-map;
302 aop_config_mem: aop-config@80880000 {
304 no-map;
307 tme_crash_dump_mem: tme-crash-dump@808a0000 {
309 no-map;
312 tme_log_mem: tme-log@808e0000 {
314 no-map;
317 uefi_log_mem: uefi-log@808e4000 {
319 no-map;
322 secdata_apss_mem: secdata-apss@808ff000 {
324 no-map;
331 no-map;
334 cpucp_fw_mem: cpucp-fw@80b00000 {
336 no-map;
339 helios_ram_dump_mem: helios-ram-dump@80c00000 {
341 no-map;
346 no-map;
351 no-map;
356 no-map;
361 no-map;
364 ipa_fw_mem: ipa-fw@8a300000 {
366 no-map;
369 ipa_gsi_mem: ipa-gsi@8a3a0000 {
371 no-map;
374 gpu_micro_code_mem: gpu-micro-code@8a31a000 {
376 no-map;
381 no-map;
384 xbl_sc_mem: xbl-sc@a6e00000 {
385 no-map;
389 global_sync_mem: global-sync@a6f00000 {
390 no-map;
394 tz_stat_mem: tz-stat@e8800000 {
395 no-map;
400 no-map;
405 no-map;
409 trusted_apps_mem: trusted-apps@e9300000 {
410 no-map;
415 smp2p-adsp {
418 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
424 qcom,local-pid = <0>;
425 qcom,remote-pid = <2>;
427 smp2p_adsp_out: master-kernel {
428 qcom,entry-name = "master-kernel";
429 #qcom,smem-state-cells = <1>;
432 smp2p_adsp_in: slave-kernel {
433 qcom,entry-name = "slave-kernel";
434 interrupt-controller;
435 #interrupt-cells = <2>;
439 smp2p-cdsp {
442 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
448 qcom,local-pid = <0>;
449 qcom,remote-pid = <5>;
451 smp2p_cdsp_out: master-kernel {
452 qcom,entry-name = "master-kernel";
453 #qcom,smem-state-cells = <1>;
456 smp2p_cdsp_in: slave-kernel {
457 qcom,entry-name = "slave-kernel";
458 interrupt-controller;
459 #interrupt-cells = <2>;
464 compatible = "simple-bus";
465 #address-cells = <2>;
466 #size-cells = <2>;
468 dma-ranges = <0 0 0 0 0x10 0>;
470 gcc: clock-controller@100000 {
471 compatible = "qcom,sar2130p-gcc";
473 #clock-cells = <1>;
474 #reset-cells = <1>;
475 #power-domain-cells = <1>;
484 compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5";
487 reg-names = "hc", "cqhci";
492 interrupt-names = "hc_irq", "pwr_irq";
497 clock-names = "iface", "core", "xo";
502 interconnect-names = "sdhc-ddr","cpu-sdhc";
503 power-domains = <&rpmhpd RPMHPD_CX>;
504 operating-points-v2 = <&sdhc1_opp_table>;
506 pinctrl-0 = <&sdc1_default>;
507 pinctrl-1 = <&sdc1_sleep>;
508 pinctrl-names = "default", "sleep";
510 bus-width = <8>;
511 non-removable;
512 supports-cqe;
514 mmc-ddr-1_8v;
515 mmc-hs200-1_8v;
516 mmc-hs400-1_8v;
517 mmc-hs400-enhanced-strobe;
521 sdhc1_opp_table: opp-table {
522 compatible = "operating-points-v2";
524 opp-100000000 {
525 opp-hz = /bits/ 64 <100000000>;
526 required-opps = <&rpmhpd_opp_low_svs>;
527 opp-peak-kBps = <500000 200000>;
528 opp-avg-kBps = <104000 0>;
531 opp-384000000 {
532 opp-hz = /bits/ 64 <384000000>;
533 required-opps = <&rpmhpd_opp_nom>;
534 opp-peak-kBps = <2500000 1000000>;
535 opp-avg-kBps = <400000 0>;
540 gpi_dma0: dma-controller@900000 {
541 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
555 #dma-cells = <3>;
556 dma-channels = <12>;
557 dma-channel-mask = <0x7e>;
564 compatible = "qcom,geni-se-qup";
566 clock-names = "m-ahb", "s-ahb";
572 interconnect-names = "qup-core";
573 #address-cells = <2>;
574 #size-cells = <2>;
580 compatible = "qcom,geni-i2c";
582 clock-names = "se";
584 pinctrl-0 = <&qup_i2c0_data_clk>;
585 pinctrl-names = "default";
587 #address-cells = <1>;
588 #size-cells = <0>;
595 interconnect-names = "qup-core", "qup-config", "qup-memory";
598 dma-names = "tx", "rx";
603 spi0: spi@980000 {
604 compatible = "qcom,geni-spi";
606 clock-names = "se";
609 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
610 pinctrl-names = "default";
617 interconnect-names = "qup-core", "qup-config", "qup-memory";
620 dma-names = "tx", "rx";
621 #address-cells = <1>;
622 #size-cells = <0>;
628 compatible = "qcom,geni-i2c";
630 clock-names = "se";
632 pinctrl-0 = <&qup_i2c1_data_clk>;
633 pinctrl-names = "default";
635 #address-cells = <1>;
636 #size-cells = <0>;
643 interconnect-names = "qup-core", "qup-config", "qup-memory";
646 dma-names = "tx", "rx";
651 spi1: spi@984000 {
652 compatible = "qcom,geni-spi";
654 clock-names = "se";
657 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
658 pinctrl-names = "default";
665 interconnect-names = "qup-core", "qup-config", "qup-memory";
668 dma-names = "tx", "rx";
669 #address-cells = <1>;
670 #size-cells = <0>;
676 compatible = "qcom,geni-i2c";
678 clock-names = "se";
680 pinctrl-0 = <&qup_i2c2_data_clk>;
681 pinctrl-names = "default";
683 #address-cells = <1>;
684 #size-cells = <0>;
691 interconnect-names = "qup-core", "qup-config", "qup-memory";
694 dma-names = "tx", "rx";
699 spi2: spi@988000 {
700 compatible = "qcom,geni-spi";
702 clock-names = "se";
705 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
706 pinctrl-names = "default";
713 interconnect-names = "qup-core", "qup-config", "qup-memory";
716 dma-names = "tx", "rx";
717 #address-cells = <1>;
718 #size-cells = <0>;
725 compatible = "qcom,geni-i2c";
727 clock-names = "se";
729 pinctrl-0 = <&qup_i2c3_data_clk>;
730 pinctrl-names = "default";
732 #address-cells = <1>;
733 #size-cells = <0>;
740 interconnect-names = "qup-core", "qup-config", "qup-memory";
743 dma-names = "tx", "rx";
748 spi3: spi@98c000 {
749 compatible = "qcom,geni-spi";
751 clock-names = "se";
754 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
755 pinctrl-names = "default";
762 interconnect-names = "qup-core", "qup-config", "qup-memory";
765 dma-names = "tx", "rx";
766 #address-cells = <1>;
767 #size-cells = <0>;
773 compatible = "qcom,geni-i2c";
775 clock-names = "se";
777 pinctrl-0 = <&qup_i2c4_data_clk>;
778 pinctrl-names = "default";
780 #address-cells = <1>;
781 #size-cells = <0>;
788 interconnect-names = "qup-core", "qup-config", "qup-memory";
791 dma-names = "tx", "rx";
796 spi4: spi@990000 {
797 compatible = "qcom,geni-spi";
799 clock-names = "se";
802 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
803 pinctrl-names = "default";
810 interconnect-names = "qup-core", "qup-config", "qup-memory";
813 dma-names = "tx", "rx";
814 #address-cells = <1>;
815 #size-cells = <0>;
821 compatible = "qcom,geni-i2c";
823 clock-names = "se";
825 pinctrl-0 = <&qup_i2c5_data_clk>;
826 pinctrl-names = "default";
828 #address-cells = <1>;
829 #size-cells = <0>;
836 interconnect-names = "qup-core", "qup-config", "qup-memory";
839 dma-names = "tx", "rx";
844 spi5: spi@994000 {
845 compatible = "qcom,geni-spi";
847 clock-names = "se";
850 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
851 pinctrl-names = "default";
858 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dma-names = "tx", "rx";
862 #address-cells = <1>;
863 #size-cells = <0>;
869 gpi_dma1: dma-controller@a00000 {
870 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
871 #dma-cells = <3>;
885 dma-channels = <12>;
886 dma-channel-mask = <0x7e>;
893 compatible = "qcom,geni-se-qup";
895 clock-names = "m-ahb", "s-ahb";
901 interconnect-names = "qup-core";
902 #address-cells = <2>;
903 #size-cells = <2>;
909 compatible = "qcom,geni-i2c";
911 clock-names = "se";
913 pinctrl-0 = <&qup_i2c6_data_clk>;
914 pinctrl-names = "default";
916 #address-cells = <1>;
917 #size-cells = <0>;
924 interconnect-names = "qup-core", "qup-config", "qup-memory";
927 dma-names = "tx", "rx";
932 spi6: spi@a80000 {
933 compatible = "qcom,geni-spi";
935 clock-names = "se";
938 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
939 pinctrl-names = "default";
946 interconnect-names = "qup-core", "qup-config", "qup-memory";
949 dma-names = "tx", "rx";
950 #address-cells = <1>;
951 #size-cells = <0>;
957 compatible = "qcom,geni-i2c";
959 clock-names = "se";
961 pinctrl-0 = <&qup_i2c7_data_clk>;
962 pinctrl-names = "default";
964 #address-cells = <1>;
965 #size-cells = <0>;
972 interconnect-names = "qup-core", "qup-config", "qup-memory";
975 dma-names = "tx", "rx";
980 spi7: spi@a84000 {
981 compatible = "qcom,geni-spi";
983 clock-names = "se";
986 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
987 pinctrl-names = "default";
994 interconnect-names = "qup-core", "qup-config", "qup-memory";
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
999 #size-cells = <0>;
1005 compatible = "qcom,geni-uart";
1007 clock-names = "se";
1009 pinctrl-0 = <&qup_uart7_default>;
1010 pinctrl-names = "default";
1016 interconnect-names = "qup-core", "qup-config";
1022 compatible = "qcom,geni-i2c";
1024 clock-names = "se";
1026 pinctrl-0 = <&qup_i2c8_data_clk>;
1027 pinctrl-names = "default";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1037 interconnect-names = "qup-core", "qup-config", "qup-memory";
1040 dma-names = "tx", "rx";
1045 spi8: spi@a88000 {
1046 compatible = "qcom,geni-spi";
1048 clock-names = "se";
1051 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1052 pinctrl-names = "default";
1059 interconnect-names = "qup-core", "qup-config", "qup-memory";
1062 dma-names = "tx", "rx";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1070 compatible = "qcom,geni-i2c";
1072 clock-names = "se";
1074 pinctrl-0 = <&qup_i2c9_data_clk>;
1075 pinctrl-names = "default";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1085 interconnect-names = "qup-core", "qup-config", "qup-memory";
1088 dma-names = "tx", "rx";
1093 spi9: spi@a8c000 {
1094 compatible = "qcom,geni-spi";
1096 clock-names = "se";
1099 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1100 pinctrl-names = "default";
1107 interconnect-names = "qup-core", "qup-config", "qup-memory";
1110 dma-names = "tx", "rx";
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1118 compatible = "qcom,geni-i2c";
1120 clock-names = "se";
1122 pinctrl-0 = <&qup_i2c10_data_clk>;
1123 pinctrl-names = "default";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1133 interconnect-names = "qup-core", "qup-config", "qup-memory";
1136 dma-names = "tx", "rx";
1141 spi10: spi@a90000 {
1142 compatible = "qcom,geni-spi";
1144 clock-names = "se";
1147 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1148 pinctrl-names = "default";
1155 interconnect-names = "qup-core", "qup-config", "qup-memory";
1158 dma-names = "tx", "rx";
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1166 compatible = "qcom,geni-i2c";
1168 clock-names = "se";
1170 pinctrl-0 = <&qup_i2c11_data_clk>;
1171 pinctrl-names = "default";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1181 interconnect-names = "qup-core", "qup-config", "qup-memory";
1184 dma-names = "tx", "rx";
1189 spi11: spi@a94000 {
1190 compatible = "qcom,geni-spi";
1192 clock-names = "se";
1195 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1196 pinctrl-names = "default";
1203 interconnect-names = "qup-core", "qup-config", "qup-memory";
1206 dma-names = "tx", "rx";
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1214 compatible = "qcom,geni-debug-uart";
1216 clock-names = "se";
1218 pinctrl-0 = <&qup_uart11_default>;
1219 pinctrl-names = "default";
1225 interconnect-names = "qup-core",
1226 "qup-config";
1233 compatible = "qcom,sar2130p-config-noc";
1235 #interconnect-cells = <2>;
1236 qcom,bcm-voters = <&apps_bcm_voter>;
1240 compatible = "qcom,sar2130p-system-noc";
1243 #interconnect-cells = <2>;
1244 qcom,bcm-voters = <&apps_bcm_voter>;
1248 compatible = "qcom,sar2130p-pcie-anoc";
1252 #interconnect-cells = <2>;
1253 qcom,bcm-voters = <&apps_bcm_voter>;
1257 compatible = "qcom,sar2130p-mmss-noc";
1259 #interconnect-cells = <2>;
1260 qcom,bcm-voters = <&apps_bcm_voter>;
1265 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
1272 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1273 #address-cells = <3>;
1274 #size-cells = <2>;
1277 bus-range = <0x00 0xff>;
1279 dma-coherent;
1281 linux,pci-domain = <0>;
1282 num-lanes = <2>;
1292 interrupt-names = "msi0",
1300 #interrupt-cells = <1>;
1301 interrupt-map-mask = <0 0 0 0x7>;
1302 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1314 clock-names = "aux",
1326 interconnect-names = "pcie-mem", "cpu-pcie";
1328 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1332 reset-names = "pci";
1334 power-domains = <&gcc PCIE_0_GDSC>;
1337 phy-names = "pciephy";
1344 bus-range = <0x01 0xff>;
1346 #address-cells = <3>;
1347 #size-cells = <2>;
1353 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
1361 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1365 reset-names = "phy";
1367 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1368 assigned-clock-rates = <100000000>;
1370 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1372 #clock-cells = <0>;
1373 clock-output-names = "pcie0_pipe_clk";
1375 #phy-cells = <0>;
1382 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
1389 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1390 #address-cells = <3>;
1391 #size-cells = <2>;
1394 bus-range = <0x00 0xff>;
1396 dma-coherent;
1398 linux,pci-domain = <1>;
1399 num-lanes = <2>;
1409 interrupt-names = "msi0",
1417 #interrupt-cells = <1>;
1418 interrupt-map-mask = <0 0 0 0x7>;
1419 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1433 clock-names = "aux",
1443 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1444 assigned-clock-rates = <19200000>;
1450 interconnect-names = "pcie-mem", "cpu-pcie";
1452 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1457 reset-names = "pci", "link_down";
1459 power-domains = <&gcc PCIE_1_GDSC>;
1462 phy-names = "pciephy";
1469 bus-range = <0x01 0xff>;
1471 #address-cells = <3>;
1472 #size-cells = <2>;
1478 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
1486 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1490 reset-names = "phy";
1492 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1493 assigned-clock-rates = <100000000>;
1495 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1497 #clock-cells = <0>;
1498 clock-output-names = "pcie1_pipe_clk";
1500 #phy-cells = <0>;
1506 compatible = "qcom,tcsr-mutex";
1509 #hwlock-cells = <1>;
1512 tcsr: clock-controller@1fc0000 {
1513 compatible = "qcom,sar2130p-tcsr", "syscon";
1516 #clock-cells = <1>;
1517 #reset-cells = <1>;
1521 compatible = "qcom,sar2130p-adsp-pas";
1524 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1529 interrupt-names = "wdog", "fatal", "ready",
1530 "handover", "stop-ack";
1533 clock-names = "xo";
1535 power-domains = <&rpmhpd RPMHPD_LCX>,
1537 power-domain-names = "lcx", "lmx";
1539 memory-region = <&adsp_mem>;
1543 qcom,smem-states = <&smp2p_adsp_out 0>;
1544 qcom,smem-state-names = "stop";
1548 remoteproc_adsp_glink: glink-edge {
1549 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1556 qcom,remote-pid = <2>;
1560 qcom,glink-channels = "adsp_apps";
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1569 #sound-dai-cells = <0>;
1570 qcom,protection-domain = "avs/audio",
1574 compatible = "qcom,q6apm-dais";
1579 compatible = "qcom,q6apm-lpass-dais";
1580 #sound-dai-cells = <1>;
1587 qcom,protection-domain = "avs/audio",
1590 q6prmcc: clock-controller {
1591 compatible = "qcom,q6prm-lpass-clocks";
1592 #clock-cells = <2>;
1599 qcom,glink-channels = "fastrpcglink-apps-dsp";
1601 qcom,non-secure-domain;
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1605 compute-cb@3 {
1606 compatible = "qcom,fastrpc-compute-cb";
1611 compute-cb@4 {
1612 compatible = "qcom,fastrpc-compute-cb";
1617 compute-cb@5 {
1618 compatible = "qcom,fastrpc-compute-cb";
1623 compute-cb@6 {
1624 compatible = "qcom,fastrpc-compute-cb";
1633 compatible = "qcom,adreno-621.0", "qcom,adreno";
1637 reg-names = "kgsl_3d0_reg_memory",
1645 operating-points-v2 = <&gpu_opp_table>;
1649 nvmem-cells = <&gpu_speed_bin>;
1650 nvmem-cell-names = "speed_bin";
1651 #cooling-cells = <2>;
1655 gpu_zap_shader: zap-shader {
1656 memory-region = <&gpu_micro_code_mem>;
1659 gpu_opp_table: opp-table {
1660 compatible = "operating-points-v2";
1662 opp-843000000 {
1663 opp-hz = /bits/ 64 <843000000>;
1664 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1665 opp-supported-hw = <0x1>;
1668 opp-780000000 {
1669 opp-hz = /bits/ 64 <780000000>;
1670 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1671 opp-supported-hw = <0x1>;
1674 opp-644000000 {
1675 opp-hz = /bits/ 64 <644000000>;
1676 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1677 opp-supported-hw = <0x3>;
1680 opp-570000000 {
1681 opp-hz = /bits/ 64 <570000000>;
1682 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1683 opp-supported-hw = <0x3>;
1686 opp-450000000 {
1687 opp-hz = /bits/ 64 <450000000>;
1688 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1689 opp-supported-hw = <0x3>;
1692 opp-320000000 {
1693 opp-hz = /bits/ 64 <320000000>;
1694 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1695 opp-supported-hw = <0x3>;
1698 opp-235000000 {
1699 opp-hz = /bits/ 64 <235000000>;
1700 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
1701 opp-supported-hw = <0x3>;
1707 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
1711 reg-names = "gmu", "rscc", "gmu_pdc";
1715 interrupt-names = "hfi", "gmu";
1723 clock-names = "ahb",
1730 power-domains = <&gpucc GPU_CX_GDSC>,
1732 power-domain-names = "cx",
1739 operating-points-v2 = <&gmu_opp_table>;
1741 gmu_opp_table: opp-table {
1742 compatible = "operating-points-v2";
1744 opp-220000000 {
1745 opp-hz = /bits/ 64 <220000000>;
1746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1749 opp-550000000 {
1750 opp-hz = /bits/ 64 <550000000>;
1751 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1756 gpucc: clock-controller@3d90000 {
1757 compatible = "qcom,sar2130p-gpucc";
1764 #clock-cells = <1>;
1765 #reset-cells = <1>;
1766 #power-domain-cells = <1>;
1770 compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu",
1771 "qcom,smmu-500", "arm,mmu-500";
1773 #iommu-cells = <2>;
1774 #global-interrupts = <1>;
1789 clock-names = "hlos",
1793 power-domains = <&gpucc GPU_CX_GDSC>;
1794 dma-coherent;
1798 compatible = "qcom,sar2130p-snps-eusb2-phy",
1799 "qcom,sm8550-snps-eusb2-phy";
1801 #phy-cells = <0>;
1804 clock-names = "ref";
1812 compatible = "qcom,sar2130p-qmp-usb3-dp-phy";
1819 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1821 power-domains = <&gcc USB3_PHY_GDSC>;
1825 reset-names = "phy", "common";
1827 #clock-cells = <1>;
1828 #phy-cells = <1>;
1830 orientation-switch;
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1849 remote-endpoint = <&usb_1_dwc3_ss>;
1863 compatible = "qcom,sar2130p-dwc3", "qcom,dwc3";
1865 #address-cells = <2>;
1866 #size-cells = <2>;
1875 clock-names = "cfg_noc",
1882 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1884 assigned-clock-rates = <19200000>, <200000000>;
1886 interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1891 interrupt-names = "pwr_event",
1897 power-domains = <&gcc USB30_PRIM_GDSC>;
1898 required-opps = <&rpmhpd_opp_nom>;
1906 interconnect-names = "usb-ddr", "apps-usb";
1917 phy-names = "usb2-phy", "usb3-phy";
1919 snps,has-lpm-erratum;
1920 snps,hird-threshold = /bits/ 8 <0x0>;
1921 snps,is-utmi-l1-suspend;
1922 snps,dis-u1-entry-quirk;
1923 snps,dis-u2-entry-quirk;
1926 snps,parkmode-disable-ss-quirk;
1928 tx-fifo-resize;
1929 dma-coherent;
1930 usb-role-switch;
1933 #address-cells = <1>;
1934 #size-cells = <0>;
1947 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
1954 pdc: interrupt-controller@b220000 {
1955 compatible = "qcom,sar2130p-pdc", "qcom,pdc";
1957 qcom,pdc-ranges = <0 480 94>,
1961 #interrupt-cells = <2>;
1962 interrupt-parent = <&intc>;
1963 interrupt-controller;
1966 aoss_qmp: power-management@c300000 {
1967 compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp";
1969 interrupt-parent = <&ipcc>;
1970 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1974 #clock-cells = <0>;
1977 tsens0: thermal-sensor@c263000 {
1978 compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2";
1984 interrupt-names = "uplow", "critical";
1985 #thermal-sensor-cells = <1>;
1989 compatible = "qcom,rpmh-stats";
1994 compatible = "qcom,sar2130p-spmi-pmic-arb",
1995 "qcom,x1e80100-spmi-pmic-arb";
1999 reg-names = "core", "chnls", "obsrvr";
2004 #address-cells = <2>;
2005 #size-cells = <2>;
2011 reg-names = "cnfg", "intr";
2013 interrupt-names = "periph_irq";
2014 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2015 interrupt-controller;
2016 #interrupt-cells = <4>;
2018 #address-cells = <2>;
2019 #size-cells = <0>;
2024 compatible = "qcom,sar2130p-ipcc", "qcom,ipcc";
2028 interrupt-controller;
2029 #interrupt-cells = <3>;
2031 #mbox-cells = <2>;
2035 compatible = "qcom,sar2130p-tlmm";
2038 gpio-controller;
2039 #gpio-cells = <2>;
2040 interrupt-controller;
2041 #interrupt-cells = <2>;
2042 gpio-ranges = <&tlmm 0 0 156>;
2043 wakeup-parent = <&pdc>;
2045 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2049 drive-strength = <2>;
2050 bias-pull-up;
2053 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2057 drive-strength = <2>;
2058 bias-pull-up;
2061 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2065 drive-strength = <2>;
2066 bias-pull-up;
2069 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2073 drive-strength = <2>;
2074 bias-pull-up;
2077 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2081 drive-strength = <2>;
2082 bias-pull-up;
2085 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2089 drive-strength = <2>;
2090 bias-pull-up;
2093 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2097 drive-strength = <2>;
2098 bias-pull-up;
2101 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
2105 drive-strength = <2>;
2106 bias-pull-up;
2109 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2113 drive-strength = <2>;
2114 bias-pull-up;
2117 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2121 drive-strength = <2>;
2122 bias-pull-up;
2125 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2129 drive-strength = <2>;
2130 bias-pull-up;
2133 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2137 drive-strength = <2>;
2138 bias-pull-up;
2141 qup_spi0_cs0: qup-spi0-cs0-state {
2144 drive-strength = <2>;
2145 bias-disable;
2148 qup_spi0_cs1: qup-spi0-cs1-state {
2151 drive-strength = <2>;
2152 bias-disable;
2155 qup_spi0_data_clk: qup-spi0-data-clk-state {
2159 drive-strength = <2>;
2160 bias-disable;
2163 qup_spi1_cs: qup-spi1-cs-state {
2166 drive-strength = <2>;
2167 bias-disable;
2170 qup_spi1_data_clk: qup-spi1-data-clk-state {
2174 drive-strength = <2>;
2175 bias-disable;
2178 qup_spi2_cs: qup-spi2-cs-state {
2181 drive-strength = <2>;
2182 bias-disable;
2185 qup_spi2_data_clk: qup-spi2-data-clk-state {
2189 drive-strength = <2>;
2190 bias-disable;
2193 qup_spi3_cs0: qup-spi3-cs0-state {
2196 drive-strength = <2>;
2197 bias-disable;
2200 qup_spi3_cs1: qup-spi3-cs1-state {
2203 drive-strength = <2>;
2204 bias-disable;
2207 qup_spi3_data_clk: qup-spi3-data-clk-state {
2211 drive-strength = <2>;
2212 bias-disable;
2215 qup_spi4_cs0: qup-spi4-cs0-state {
2218 drive-strength = <2>;
2219 bias-disable;
2222 qup_spi4_cs1: qup-spi4-cs1-state {
2225 drive-strength = <2>;
2226 bias-disable;
2229 qup_spi4_data_clk: qup-spi4-data-clk-state {
2233 drive-strength = <2>;
2234 bias-disable;
2237 qup_spi5_cs: qup-spi5-cs-state {
2240 drive-strength = <2>;
2241 bias-disable;
2244 qup_spi5_data_clk: qup-spi5-data-clk-state {
2248 drive-strength = <2>;
2249 bias-disable;
2252 qup_spi6_cs: qup-spi6-cs-state {
2255 drive-strength = <2>;
2256 bias-disable;
2259 qup_spi6_data_clk: qup-spi6-data-clk-state {
2263 drive-strength = <2>;
2264 bias-disable;
2267 qup_spi7_cs: qup-spi7-cs-state {
2270 drive-strength = <2>;
2271 bias-disable;
2274 qup_spi7_data_clk: qup-spi7-data-clk-state {
2278 drive-strength = <2>;
2279 bias-disable;
2282 qup_spi8_cs: qup-spi8-cs-state {
2285 drive-strength = <2>;
2286 bias-disable;
2289 qup_spi8_data_clk: qup-spi8-data-clk-state {
2293 drive-strength = <2>;
2294 bias-disable;
2297 qup_spi9_cs: qup-spi9-cs-state {
2300 drive-strength = <2>;
2301 bias-disable;
2304 qup_spi9_data_clk: qup-spi9-data-clk-state {
2308 drive-strength = <2>;
2309 bias-disable;
2312 qup_spi10_cs: qup-spi10-cs-state {
2315 drive-strength = <2>;
2316 bias-disable;
2319 qup_spi10_data_clk: qup-spi10-data-clk-state {
2323 drive-strength = <2>;
2324 bias-disable;
2327 qup_spi11_cs: qup-spi11-cs-state {
2330 drive-strength = <2>;
2331 bias-disable;
2334 qup_spi11_data_clk: qup-spi11-data-clk-state {
2338 drive-strength = <2>;
2339 bias-disable;
2342 qup_uart7_default: qup-uart7-default-state {
2343 cts-pins {
2346 drive-strength = <2>;
2347 bias-disable;
2350 rts-pins {
2353 drive-strength = <2>;
2354 bias-pull-down;
2357 rx-pins {
2360 drive-strength = <2>;
2361 bias-pull-down;
2364 tx-pins {
2367 drive-strength = <2>;
2368 bias-pull-up;
2372 qup_uart11_default: qup-uart11-default-state {
2375 drive-strength = <2>;
2376 bias-disable;
2379 sdc1_default: sdc1-default-state {
2380 clk-pins {
2382 drive-strength = <16>;
2383 bias-disable;
2386 cmd-pins {
2388 drive-strength = <10>;
2389 bias-pull-up;
2392 data-pins {
2394 drive-strength = <10>;
2395 bias-pull-up;
2398 rclk-pins {
2400 bias-pull-down;
2404 sdc1_sleep: sdc1-sleep-state {
2405 clk-pins {
2407 drive-strength = <2>;
2408 bias-disable;
2411 cmd-pins {
2413 drive-strength = <2>;
2414 bias-pull-up;
2417 data-pins {
2419 drive-strength = <2>;
2420 bias-pull-up;
2423 rclk-pins {
2425 bias-pull-down;
2431 compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2433 #iommu-cells = <2>;
2434 #global-interrupts = <1>;
2532 dma-coherent;
2535 intc: interrupt-controller@17200000 {
2536 compatible = "arm,gic-v3";
2537 #interrupt-cells = <3>;
2538 interrupt-controller;
2539 #redistributor-regions = <1>;
2540 redistributor-stride = <0x0 0x20000>;
2544 #address-cells = <2>;
2545 #size-cells = <2>;
2548 gic_its: msi-controller@17240000 {
2549 compatible = "arm,gic-v3-its";
2551 msi-controller;
2552 #msi-cells = <1>;
2558 compatible = "qcom,rpmh-rsc";
2562 reg-names = "drv-0", "drv-1", "drv-2";
2566 qcom,tcs-offset = <0xd00>;
2567 qcom,drv-id = <2>;
2568 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
2570 power-domains = <&cluster_pd>;
2572 apps_bcm_voter: bcm-voter {
2573 compatible = "qcom,bcm-voter";
2576 rpmhcc: clock-controller {
2577 compatible = "qcom,sar2130p-rpmh-clk";
2578 #clock-cells = <1>;
2579 clock-names = "xo";
2583 rpmhpd: power-controller {
2584 compatible = "qcom,sar2130p-rpmhpd";
2585 #power-domain-cells = <1>;
2586 operating-points-v2 = <&rpmhpd_opp_table>;
2588 rpmhpd_opp_table: opp-table {
2589 compatible = "operating-points-v2";
2592 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2596 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2600 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2604 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2608 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2612 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2616 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2620 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2624 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2631 compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss";
2633 reg-names = "freq-domain0";
2635 clock-names = "xo", "alternate";
2637 interrupt-names = "dcvsh-irq-0";
2638 #freq-domain-cells = <1>;
2639 #clock-cells = <1>;
2643 compatible = "qcom,sar2130p-gem-noc";
2645 #interconnect-cells = <2>;
2646 qcom,bcm-voters = <&apps_bcm_voter>;
2650 * Bootloader expects just cache-controller node instead of
2651 * the typical system-cache-controller
2653 llcc: cache-controller@19200000 {
2654 compatible = "qcom,sar2130p-llcc";
2661 reg-names = "llcc0_base",
2671 compatible = "qcom,sar2130p-qfprom", "qcom,qfprom";
2673 #address-cells = <1>;
2674 #size-cells = <1>;
2675 read-only;
2677 gpu_speed_bin: gpu-speed-bin@119 {
2684 compatible = "qcom,sar2130p-nsp-noc";
2686 #interconnect-cells = <2>;
2687 qcom,bcm-voters = <&apps_bcm_voter>;
2691 compatible = "qcom,sar2130p-lpass-ag-noc";
2693 #interconnect-cells = <1>;
2694 qcom,bcm-voters = <&apps_bcm_voter>;
2699 compatible = "arm,armv8-timer";
2707 thermal-zones {
2708 aoss0-thermal {
2709 thermal-sensors = <&tsens0 0>;
2712 trip-point0 {
2718 aoss0-critical {
2727 cpu0-thermal {
2728 thermal-sensors = <&tsens0 1>;
2731 cpu0_alert0: trip-point0 {
2737 cpu0_alert1: trip-point1 {
2743 cpu0-critical {
2750 cooling-maps {
2753 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2761 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2769 cpu1-thermal {
2770 thermal-sensors = <&tsens0 2>;
2773 cpu1_alert0: trip-point0 {
2779 cpu1_alert1: trip-point1 {
2785 cpu1-critical {
2792 cooling-maps {
2795 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2803 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2811 cpu2-thermal {
2812 thermal-sensors = <&tsens0 3>;
2815 cpu2_alert0: trip-point0 {
2821 cpu2_alert1: trip-point1 {
2827 cpu2-critical {
2834 cooling-maps {
2837 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2845 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2853 cpu3-thermal {
2854 thermal-sensors = <&tsens0 4>;
2857 cpu3_alert0: trip-point0 {
2863 cpu3_alert1: rip-point1 {
2869 cpu3-critical {
2876 cooling-maps {
2879 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2887 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2895 gpuss0-thermal {
2896 polling-delay-passive = <250>;
2898 thermal-sensors = <&tsens0 5>;
2900 cooling-maps {
2903 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2908 gpu0_alert0: trip-point0 {
2914 trip-point1 {
2920 trip-point2 {
2928 gpuss1-thermal {
2929 polling-delay-passive = <250>;
2931 thermal-sensors = <&tsens0 6>;
2933 cooling-maps {
2936 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2941 gpu1_alert0: trip-point0 {
2947 trip-point1 {
2953 trip-point2 {
2961 nspss0-thermal {
2962 thermal-sensors = <&tsens0 7>;
2965 trip-point0 {
2971 trip-point1 {
2977 nspss1-critical {
2985 nspss1-thermal {
2986 thermal-sensors = <&tsens0 8>;
2989 trip-point0 {
2995 trip-point1 {
3001 nspss2-critical {
3009 nspss2-thermal {
3010 thermal-sensors = <&tsens0 9>;
3013 trip-point0 {
3019 trip-point1 {
3025 nspss2-critical {
3033 video-thermal {
3034 thermal-sensors = <&tsens0 10>;
3037 trip-point0 {
3043 video-critical {
3051 ddr-thermal {
3052 thermal-sensors = <&tsens0 11>;
3055 trip-point0 {
3061 ddr-critical {
3069 camera0-thermal {
3070 thermal-sensors = <&tsens0 12>;
3073 trip-point0 {
3079 camera0-critical {
3087 camera1-thermal {
3088 thermal-sensors = <&tsens0 13>;
3091 trip-point0 {
3097 camera1-critical {
3105 mdmss-thermal {
3106 thermal-sensors = <&tsens0 14>;
3109 trip-point0 {
3115 mdmss-critical {