Lines Matching +full:0 +full:x80c00000
33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
78 clocks = <&cpufreq_hw 0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
97 reg = <0x0 0x200>;
98 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
157 cpu_sleep_0: cpu-sleep-0-0 {
160 arm,psci-suspend-param = <0x40000003>;
167 cpu_sleep_1: cpu-sleep-0-1 {
170 arm,psci-suspend-param = <0x40000004>;
179 cluster_sleep_0: cluster-sleep-0 {
181 arm,psci-suspend-param = <0x41000044>;
189 arm,psci-suspend-param = <0x41002344>;
197 arm,psci-suspend-param = <0x4100c344>;
208 qcom,dload-mode = <&tcsr_mutex 0x13000>;
214 clk_virt: interconnect-0 {
229 reg = <0x0 0x80000000 0x0 0x0>;
242 #power-domain-cells = <0>;
248 #power-domain-cells = <0>;
254 #power-domain-cells = <0>;
260 #power-domain-cells = <0>;
266 #power-domain-cells = <0>;
277 reg = <0x0 0x80000000 0x0 0x600000>;
282 reg = <0x0 0x80600000 0x0 0x40000>;
287 reg = <0x0 0x80640000 0x0 0x1c0000>;
292 reg = <0x0 0x80800000 0x0 0x60000>;
298 reg = <0x0 0x80860000 0x0 0x20000>;
303 reg = <0x0 0x80880000 0x0 0x20000>;
308 reg = <0x0 0x808a0000 0x0 0x40000>;
313 reg = <0x0 0x808e0000 0x0 0x4000>;
318 reg = <0x0 0x808e4000 0x0 0x10000>;
323 reg = <0x0 0x808ff000 0x0 0x1000>;
329 reg = <0x0 0x80900000 0x0 0x200000>;
335 reg = <0x0 0x80b00000 0x0 0x100000>;
340 reg = <0x0 0x80c00000 0x0 0xe00000>;
345 reg = <0x0 0x84e00000 0x0 0x800000>;
350 reg = <0x0 0x86f00000 0x0 0x500000>;
355 reg = <0x0 0x87600000 0x0 0x1e00000>;
360 reg = <0x0 0x89400000 0x0 0xf00000>;
365 reg = <0x0 0x8a300000 0x0 0x10000>;
370 reg = <0x0 0x8a310000 0x0 0xa000>;
375 reg = <0x0 0x8a31a000 0x0 0x2000>;
380 reg = <0x0 0x8a400000 0x0 0x700000>;
386 reg = <0x0 0xa6e00000 0x0 0x40000>;
391 reg = <0x0 0xa6f00000 0x0 0x100000>;
396 reg = <0x0 0xe8800000 0x0 0x100000>;
401 reg = <0x0 0xe8900000 0x0 0x500000>;
406 reg = <0x0 0xe8e00000 0x0 0x500000>;
411 reg = <0x0 0xe9300000 0x0 0xc00000>;
424 qcom,local-pid = <0>;
448 qcom,local-pid = <0>;
463 soc: soc@0 {
467 ranges = <0 0 0 0 0x10 0>;
468 dma-ranges = <0 0 0 0 0x10 0>;
472 reg = <0x0 0x00100000 0x0 0x1f4200>;
485 reg = <0x0 0x007c4000 0x0 0x1000>,
486 <0x0 0x007c5000 0x0 0x1000>;
489 iommus = <&apps_smmu 0x160 0x0>;
506 pinctrl-0 = <&sdc1_default>;
528 opp-avg-kBps = <104000 0>;
535 opp-avg-kBps = <400000 0>;
542 reg = <0x0 0x00900000 0x0 0x60000>;
557 dma-channel-mask = <0x7e>;
558 iommus = <&apps_smmu 0x76 0x0>;
565 reg = <0x0 0x009c0000 0x0 0x2000>;
569 iommus = <&apps_smmu 0x63 0x0>;
581 reg = <0x0 0x00980000 0x0 0x4000>;
584 pinctrl-0 = <&qup_i2c0_data_clk>;
588 #size-cells = <0>;
596 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
597 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
605 reg = <0x0 0x00980000 0x0 0x4000>;
609 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
618 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
619 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
622 #size-cells = <0>;
629 reg = <0x0 0x00984000 0x0 0x4000>;
632 pinctrl-0 = <&qup_i2c1_data_clk>;
636 #size-cells = <0>;
644 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
653 reg = <0x0 0x00984000 0x0 0x4000>;
657 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
666 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
670 #size-cells = <0>;
677 reg = <0x0 0x00988000 0x0 0x4000>;
680 pinctrl-0 = <&qup_i2c2_data_clk>;
684 #size-cells = <0>;
692 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
701 reg = <0x0 0x00988000 0x0 0x4000>;
705 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
714 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
718 #size-cells = <0>;
726 reg = <0x0 0x0098c000 0x0 0x4000>;
729 pinctrl-0 = <&qup_i2c3_data_clk>;
733 #size-cells = <0>;
741 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
750 reg = <0x0 0x0098c000 0x0 0x4000>;
754 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
763 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
767 #size-cells = <0>;
774 reg = <0x0 0x00990000 0x0 0x4000>;
777 pinctrl-0 = <&qup_i2c4_data_clk>;
781 #size-cells = <0>;
789 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
798 reg = <0x0 0x00990000 0x0 0x4000>;
802 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
811 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
815 #size-cells = <0>;
822 reg = <0x0 0x00994000 0x0 0x4000>;
825 pinctrl-0 = <&qup_i2c5_data_clk>;
829 #size-cells = <0>;
837 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
846 reg = <0x0 0x00994000 0x0 0x4000>;
850 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
859 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
863 #size-cells = <0>;
872 reg = <0x0 0x00a00000 0x0 0x60000>;
886 dma-channel-mask = <0x7e>;
887 iommus = <&apps_smmu 0x16 0x0>;
894 reg = <0x0 0x00ac0000 0x0 0x6000>;
898 iommus = <&apps_smmu 0x3 0x0>;
910 reg = <0x0 0x00a80000 0x0 0x4000>;
913 pinctrl-0 = <&qup_i2c6_data_clk>;
917 #size-cells = <0>;
925 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
926 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
934 reg = <0x0 0x00a80000 0x0 0x4000>;
938 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
947 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
948 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
951 #size-cells = <0>;
958 reg = <0x0 0x00a84000 0x0 0x4000>;
961 pinctrl-0 = <&qup_i2c7_data_clk>;
965 #size-cells = <0>;
973 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
982 reg = <0x0 0x00a84000 0x0 0x4000>;
986 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
995 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
999 #size-cells = <0>;
1006 reg = <0x0 0x00a84000 0x0 0x4000>;
1009 pinctrl-0 = <&qup_uart7_default>;
1023 reg = <0x0 0x00a88000 0x0 0x4000>;
1026 pinctrl-0 = <&qup_i2c8_data_clk>;
1030 #size-cells = <0>;
1038 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1047 reg = <0x0 0x00a88000 0x0 0x4000>;
1051 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1060 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1064 #size-cells = <0>;
1071 reg = <0x0 0x00a8c000 0x0 0x4000>;
1074 pinctrl-0 = <&qup_i2c9_data_clk>;
1078 #size-cells = <0>;
1086 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1095 reg = <0x0 0x00a8c000 0x0 0x4000>;
1099 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1108 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1112 #size-cells = <0>;
1119 reg = <0x0 0x00a90000 0x0 0x4000>;
1122 pinctrl-0 = <&qup_i2c10_data_clk>;
1126 #size-cells = <0>;
1134 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1143 reg = <0x0 0x00a90000 0x0 0x4000>;
1147 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1156 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1160 #size-cells = <0>;
1167 reg = <0x0 0x00a94000 0x0 0x4000>;
1170 pinctrl-0 = <&qup_i2c11_data_clk>;
1174 #size-cells = <0>;
1182 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1191 reg = <0x0 0x00a94000 0x0 0x4000>;
1195 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1204 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1208 #size-cells = <0>;
1215 reg = <0x0 0x00a94000 0x0 0x4000>;
1218 pinctrl-0 = <&qup_uart11_default>;
1234 reg = <0x0 0x01500000 0x0 0x10>;
1241 reg = <0x0 0x01680000 0x0 0x29080>;
1249 reg = <0x0 0x016c0000 0x0 0xa080>;
1258 reg = <0x0 0x01740000 0x0 0x1f100>;
1266 reg = <0x0 0x01c00000 0x0 0x3000>,
1267 <0x0 0x60000000 0x0 0xf1d>,
1268 <0x0 0x60000f20 0x0 0xa8>,
1269 <0x0 0x60001000 0x0 0x1000>,
1270 <0x0 0x60100000 0x0 0x100000>,
1271 <0x0 0x01c0c000 0x0 0x1000>;
1275 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1276 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1277 bus-range = <0x00 0xff>;
1281 linux,pci-domain = <0>;
1301 interrupt-map-mask = <0 0 0 0x7>;
1302 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1303 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1304 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1305 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1328 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1329 <0x100 &apps_smmu 0x1c01 0x1>;
1341 pcieport0: pcie@0 {
1343 reg = <0x0 0x0 0x0 0x0 0x0>;
1344 bus-range = <0x01 0xff>;
1354 reg = <0x0 0x01c06000 0x0 0x2000>;
1372 #clock-cells = <0>;
1375 #phy-cells = <0>;
1383 reg = <0x0 0x01c08000 0x0 0x3000>,
1384 <0x0 0x40000000 0x0 0xf1d>,
1385 <0x0 0x40000f20 0x0 0xa8>,
1386 <0x0 0x40001000 0x0 0x1000>,
1387 <0x0 0x40100000 0x0 0x100000>,
1388 <0x0 0x01c0b000 0x0 0x1000>;
1392 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1393 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1394 bus-range = <0x00 0xff>;
1418 interrupt-map-mask = <0 0 0 0x7>;
1419 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1420 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1421 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1422 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1452 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1453 <0x100 &apps_smmu 0x1e01 0x1>;
1466 pcie@0 {
1468 reg = <0x0 0x0 0x0 0x0 0x0>;
1469 bus-range = <0x01 0xff>;
1479 reg = <0x0 0x01c0e000 0x0 0x2000>;
1497 #clock-cells = <0>;
1500 #phy-cells = <0>;
1507 reg = <0x0 0x01f40000 0x0 0x20000>;
1514 reg = <0x0 0x01fc0000 0x0 0x30000>;
1522 reg = <0x0 0x03000000 0x0 0x10000>;
1525 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1543 qcom,smem-states = <&smp2p_adsp_out 0>;
1564 #size-cells = <0>;
1569 #sound-dai-cells = <0>;
1575 iommus = <&apps_smmu 0x1801 0x0>;
1603 #size-cells = <0>;
1608 iommus = <&apps_smmu 0x1803 0x0>;
1614 iommus = <&apps_smmu 0x1804 0x0>;
1620 iommus = <&apps_smmu 0x1805 0x0>;
1626 iommus = <&apps_smmu 0x1806 0x0>;
1634 reg = <0x0 0x03d00000 0x0 0x40000>,
1635 <0x0 0x03d9e000 0x0 0x2000>,
1636 <0x0 0x03d61000 0x0 0x800>;
1643 iommus = <&adreno_smmu 0 0x401>;
1665 opp-supported-hw = <0x1>;
1671 opp-supported-hw = <0x1>;
1677 opp-supported-hw = <0x3>;
1683 opp-supported-hw = <0x3>;
1689 opp-supported-hw = <0x3>;
1695 opp-supported-hw = <0x3>;
1701 opp-supported-hw = <0x3>;
1708 reg = <0x0 0x03d6a000 0x0 0x35000>,
1709 <0x0 0x03de0000 0x0 0x10000>,
1710 <0x0 0x0b290000 0x0 0x10000>;
1735 iommus = <&adreno_smmu 5 0x400>;
1758 reg = <0x0 0x03d90000 0x0 0xa000>;
1772 reg = <0x0 0x03da0000 0x0 0x10000>;
1800 reg = <0x0 0x088e3000 0x0 0x154>;
1801 #phy-cells = <0>;
1813 reg = <0x0 0x088e8000 0x0 0x3000>;
1836 #size-cells = <0>;
1838 port@0 {
1839 reg = <0>;
1864 reg = <0x0 0x0a6f8800 0x0 0x400>;
1912 reg = <0x0 0x0a600000 0x0 0xcd00>;
1914 iommus = <&apps_smmu 0x20 0x0>;
1920 snps,hird-threshold = /bits/ 8 <0x0>;
1934 #size-cells = <0>;
1936 port@0 {
1937 reg = <0>;
1956 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
1957 qcom,pdc-ranges = <0 480 94>,
1968 reg = <0x0 0x0c300000 0x0 0x400>;
1974 #clock-cells = <0>;
1979 reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */
1980 <0x0 0x0c222000 0x0 0x1000>; /* SROT */
1990 reg = <0x0 0x0c3f0000 0x0 0x400>;
1996 reg = <0x0 0x0c400000 0x0 0x3000>,
1997 <0x0 0x0c500000 0x0 0x400000>,
1998 <0x0 0x0c440000 0x0 0x80000>;
2001 qcom,ee = <0>;
2002 qcom,channel = <0>;
2009 reg = <0x0 0x0c42d000 0x0 0x4000>,
2010 <0x0 0x0c4c0000 0x0 0x10000>;
2019 #size-cells = <0>;
2025 reg = <0x0 0x0ed18000 0x0 0x1000>;
2036 reg = <0x0 0x0f100000 0x0 0x300000>;
2042 gpio-ranges = <&tlmm 0 0 156>;
2432 reg = <0x0 0x15000000 0x0 0x100000>;
2540 redistributor-stride = <0x0 0x20000>;
2541 reg = <0x0 0x17200000 0x0 0x10000>,
2542 <0x0 0x17260000 0x0 0x100000>;
2550 reg = <0x0 0x17240000 0x0 0x20000>;
2559 reg = <0x0 0x17a00000 0x0 0x10000>,
2560 <0x0 0x17a10000 0x0 0x10000>,
2561 <0x0 0x17a20000 0x0 0x10000>;
2562 reg-names = "drv-0", "drv-1", "drv-2";
2566 qcom,tcs-offset = <0xd00>;
2569 <WAKE_TCS 2>, <CONTROL_TCS 0>;
2632 reg = <0x0 0x17d91000 0x0 0x1000>;
2637 interrupt-names = "dcvsh-irq-0";
2644 reg = <0x0 0x19100000 0x0 0xa2080>;
2655 reg = <0x0 0x19200000 0x0 0x80000>,
2656 <0x0 0x19300000 0x0 0x80000>,
2657 <0x0 0x19a00000 0x0 0x80000>,
2658 <0x0 0x19c00000 0x0 0x80000>,
2659 <0x0 0x19af0000 0x0 0x80000>,
2660 <0x0 0x19cf0000 0x0 0x80000>;
2672 reg = <0x0 0x221c8000 0x0 0x1000>;
2678 reg = <0x119 0x2>;
2685 reg = <0x0 0x320c0000 0x0 0x10>;
2692 reg = <0x0 0x3c40000 0x0 0x10>;
2709 thermal-sensors = <&tsens0 0>;
2720 hysteresis = <0>;
3045 hysteresis = <0>;
3063 hysteresis = <0>;
3081 hysteresis = <0>;
3099 hysteresis = <0>;
3117 hysteresis = <0>;