Lines Matching +full:hs400 +full:- +full:ds +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
20 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
28 stdout-path = "serial0:921600n8";
33 compatible = "linaro,optee-tz";
38 gpio-keys {
39 compatible = "gpio-keys";
40 pinctrl-names = "default";
41 pinctrl-0 = <&gpio_keys>;
43 key-volume-up {
47 wakeup-source;
48 debounce-interval = <15>;
57 usb_otg_vbus: regulator-0 {
58 compatible = "regulator-fixed";
59 regulator-name = "otg_vbus";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
63 enable-active-high;
66 reserved-memory {
67 #address-cells = <2>;
68 #size-cells = <2>;
73 no-map;
77 /* 12 MiB reserved for OP-TEE (BL32)
78 * +-----------------------+ 0x43e0_0000
80 * +-----------------------+ 0x43c0_0000
82 * + TZDRAM +--------------+ 0x4340_0000
84 * +-----------------------+ 0x4320_0000
87 no-map;
93 compatible = "mediatek,mt8365-mt6357";
94 pinctrl-names = "default",
100 pinctrl-0 = <&aud_default_pins>;
101 pinctrl-1 = <&aud_dmic_pins>;
102 pinctrl-2 = <&aud_miso_off_pins>;
103 pinctrl-3 = <&aud_miso_on_pins>;
104 pinctrl-4 = <&aud_mosi_off_pins>;
105 pinctrl-5 = <&aud_mosi_on_pins>;
111 mediatek,dmic-mode = <1>;
116 proc-supply = <&mt6357_vproc_reg>;
117 sram-supply = <&mt6357_vsram_proc_reg>;
121 proc-supply = <&mt6357_vproc_reg>;
122 sram-supply = <&mt6357_vsram_proc_reg>;
126 proc-supply = <&mt6357_vproc_reg>;
127 sram-supply = <&mt6357_vsram_proc_reg>;
131 proc-supply = <&mt6357_vproc_reg>;
132 sram-supply = <&mt6357_vsram_proc_reg>;
136 pinctrl-0 = <ðernet_pins>;
137 pinctrl-names = "default";
138 phy-handle = <ð_phy>;
139 phy-mode = "rmii";
149 #address-cells = <1>;
150 #size-cells = <0>;
152 eth_phy: ethernet-phy@0 {
159 clock-frequency = <100000>;
160 pinctrl-0 = <&i2c0_pins>;
161 pinctrl-names = "default";
166 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
167 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
168 bus-width = <8>;
169 cap-mmc-highspeed;
170 cap-mmc-hw-reset;
171 hs400-ds-delay = <0x12012>;
172 max-frequency = <200000000>;
173 mmc-hs200-1_8v;
174 mmc-hs400-1_8v;
175 no-sd;
176 no-sdio;
177 non-removable;
178 pinctrl-0 = <&mmc0_default_pins>;
179 pinctrl-1 = <&mmc0_uhs_pins>;
180 pinctrl-names = "default", "state_uhs";
181 vmmc-supply = <&mt6357_vemc_reg>;
182 vqmmc-supply = <&mt6357_vio18_reg>;
187 bus-width = <4>;
188 cap-sd-highspeed;
189 cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
190 max-frequency = <200000000>;
191 pinctrl-0 = <&mmc1_default_pins>;
192 pinctrl-1 = <&mmc1_uhs_pins>;
193 pinctrl-names = "default", "state_uhs";
194 sd-uhs-sdr104;
195 sd-uhs-sdr50;
196 vmmc-supply = <&mt6357_vmch_reg>;
197 vqmmc-supply = <&mt6357_vmc_reg>;
202 interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 mediatek,micbias0-microvolt = <1900000>;
206 mediatek,micbias1-microvolt = <1700000>;
210 aud_default_pins: audiodefault-pins {
211 clk-dat-pins {
219 aud_dmic_pins: audiodmic-pins {
220 clk-dat-pins {
227 aud_miso_off_pins: misooff-pins {
228 clk-dat-pins {
233 input-enable;
234 bias-pull-down;
235 drive-strength = <2>;
239 aud_miso_on_pins: misoon-pins {
240 clk-dat-pins {
245 drive-strength = <6>;
249 aud_mosi_off_pins: mosioff-pins {
250 clk-dat-pins {
255 input-enable;
256 bias-pull-down;
257 drive-strength = <2>;
261 aud_mosi_on_pins: mosion-pins {
262 clk-dat-pins {
267 drive-strength = <6>;
271 ethernet_pins: ethernet-pins {
296 gpio_keys: gpio-keys-pins {
299 bias-pull-up;
300 input-enable;
304 i2c0_pins: i2c0-pins {
308 bias-pull-up;
312 mmc0_default_pins: mmc0-default-pins {
313 clk-pins {
315 bias-pull-down;
318 cmd-dat-pins {
328 input-enable;
329 bias-pull-up;
332 rst-pins {
334 bias-pull-up;
338 mmc0_uhs_pins: mmc0-uhs-pins {
339 clk-pins {
341 drive-strength = <MTK_DRIVE_10mA>;
342 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
345 cmd-dat-pins {
355 input-enable;
356 drive-strength = <MTK_DRIVE_10mA>;
357 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
360 ds-pins {
362 drive-strength = <MTK_DRIVE_10mA>;
363 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
366 rst-pins {
368 drive-strength = <MTK_DRIVE_10mA>;
369 bias-pull-up;
373 mmc1_default_pins: mmc1-default-pins {
374 cd-pins {
376 bias-pull-up;
379 clk-pins {
381 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
384 cmd-dat-pins {
390 input-enable;
391 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
395 mmc1_uhs_pins: mmc1-uhs-pins {
396 clk-pins {
398 drive-strength = <8>;
399 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
402 cmd-dat-pins {
408 input-enable;
409 drive-strength = <6>;
410 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
414 uart0_pins: uart0-pins {
421 uart1_pins: uart1-pins {
428 uart2_pins: uart2-pins {
435 usb_pins: usb-pins {
436 id-pins {
438 input-enable;
439 bias-pull-up;
442 usb0-vbus-pins {
444 output-high;
447 usb1-vbus-pins {
449 output-high;
453 pwm_pins: pwm-pins {
462 pinctrl-0 = <&pwm_pins>;
463 pinctrl-names = "default";
469 maximum-speed = "high-speed";
470 pinctrl-0 = <&usb_pins>;
471 pinctrl-names = "default";
472 usb-role-switch;
473 vusb33-supply = <&mt6357_vusb33_reg>;
477 compatible = "gpio-usb-b-connector", "usb-b-connector";
478 id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
480 vbus-supply = <&usb_otg_vbus>;
485 vusb33-supply = <&mt6357_vusb33_reg>;
490 pinctrl-0 = <&uart0_pins>;
491 pinctrl-names = "default";
496 pinctrl-0 = <&uart1_pins>;
497 pinctrl-names = "default";
502 pinctrl-0 = <&uart2_pins>;
503 pinctrl-names = "default";