Lines Matching +full:0 +full:x71
22 pinctrl-0 = <&pinctrl_enet2>;
30 #size-cells = <0>;
32 ethphy2_0: ethernet-phy@0 {
34 reg = <0>;
36 pinctrl-0 = <&pinctrl_enet2_phy>;
68 pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>;
72 <MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02>,
73 <MX7D_PAD_SD2_WP__ENET2_MDC 0x00>,
74 <MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71>,
75 <MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71>,
76 <MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71>,
77 <MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71>,
78 <MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71>,
79 <MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71>,
80 <MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79>,
81 <MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79>,
82 <MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79>,
83 <MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79>,
84 <MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79>,
85 <MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79>;
91 <MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070>,
93 <MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078>;
99 <MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70>,
101 <MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70>;
107 <MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70>;
114 <MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c>,
115 <MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59>;
121 pinctrl-0 = <&pinctrl_pcie>;
131 pinctrl-0 = <&pinctrl_usbotg2>;