Lines Matching +full:phy +full:- +full:ref +full:- +full:clk

1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Felipe Balbi <[email protected]>
14   be presented as a standalone DT node with an optional vendor-specific
18   - $ref: snps,dwc3-common.yaml#
24         - const: snps,dwc3
25         - const: synopsys,dwc3
38   interrupt-names:
42       - const: dwc_usb3
43       - items:
49       SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
50       PHY is suspended. suspend clocks a small part of the USB3 core when
51       SS PHY in P3. But particular cases may differ from that having less
54   clock-names:
57         - enum: [bus_early, ref, suspend]
58         - true
60   dma-coherent: true
65   power-domains:
67       The DWC3 has 2 power-domains. The power management unit (PMU) and
72       - description: Core
73       - description: Power management unit
81   - compatible
82   - reg
83   - interrupts
86   - |
91       usb-phy = <&usb2_phy>, <&usb3_phy>;
92       snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
94   - |
99       clocks = <&clk 1>, <&clk 2>, <&clk 3>;
100       clock-names = "bus_early", "ref", "suspend";
102       phy-names = "usb2-phy", "usb3-phy";