Lines Matching +full:phy +full:- +full:3 +full:p0 +full:- +full:supply
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <[email protected]>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
35 usb-phy:
38 - description: USB2/HS PHY
39 - description: USB3/SS PHY
45 phy-names:
49 - items:
50 enum: [ usb2-phy, usb3-phy ]
51 - items:
52 pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
54 snps,usb2-lpm-disable:
63 snps,usb2-gadget-lpm-disable:
68 snps,dis-start-transfer-quirk:
70 When set, disable isoc START TRANSFER command failure SW work-around
71 for DWC_usb31 version 1.70a-ea06 and prior.
80 snps,has-lpm-erratum:
84 snps,lpm-nyet-threshold:
108 description: When set core will delay PHY power change from P0 to P1/P2/P3.
122 description: When set core will set Tx de-emphasis value
127 The value driven to the PHY is controlled by the LTSSM during USB3
131 - 0 # -6dB de-emphasis
132 - 1 # -3.5dB de-emphasis
133 - 2 # No de-emphasis
136 description: When set core will disable USB3 suspend phy
140 description: When set core will disable USB2 suspend phy
146 to the PHY.
149 snps,dis-u1-entry-quirk:
153 snps,dis-u2-entry-quirk:
159 When set core will disable receiver detection in PHY P3 power state.
162 snps,dis-u2-freeclk-exists-quirk:
165 PHY doesn't provide a free-running PHY clock.
168 snps,dis-del-phy-power-chg-quirk:
170 When set core will change PHY power from P0 to P1/P2/P3 without delay.
173 snps,dis-tx-ipgap-linecheck-quirk:
177 snps,parkmode-disable-ss-quirk:
182 snps,parkmode-disable-hs-quirk:
193 snps,dis-split-quirk:
196 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
199 snps,gfladj-refclk-lpm-sel-quirk:
204 snps,resume-hs-terminations:
211 snps,ulpi-ext-vbus-drv:
213 Some ULPI USB PHY does not support internal VBUS supply, and driving
215 bit. When set, the xhci host will configure the USB2 PHY drives VBUS
216 with an external supply.
219 snps,is-utmi-l1-suspend:
225 snps,hird-threshold:
231 High-Speed PHY interface selection between UTMI+ and ULPI when the
232 DWC_USB3_HSPHY_INTERFACE has value 3.
236 snps,quirk-frame-length-adjustment:
238 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
245 snps,ref-clock-period-ns:
256 snps,rx-thr-num-pkt:
263 flow-controlled endpoint. It is only used for SuperSpeed.
270 snps,rx-max-burst:
286 snps,tx-thr-num-pkt:
299 snps,tx-max-burst:
312 snps,rx-thr-num-pkt-prd:
315 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
321 snps,rx-max-burst-prd:
324 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
330 snps,tx-thr-num-pkt-prd:
333 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
334 programming guide section 1.2.3) to enable periodic ESS TX threshold.
339 snps,tx-max-burst-prd:
342 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
343 programming guide section 1.2.3) to enable periodic ESS TX threshold.
348 tx-fifo-resize:
356 tx-fifo-max-num:
362 minimum: 3
364 snps,incr-burst-type-adjustment:
371 $ref: /schemas/types.yaml#/definitions/uint32-array
378 num-hc-interrupters:
385 This port is used with the 'usb-role-switch' property to connect the
392 controller using the OF graph bindings specified if the "usb-role-switch"
404 wakeup-source:
410 - compatible
411 - reg