Lines Matching +full:sa8775p +full:- +full:gcc
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Andy Gross <[email protected]>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,qcs615-ufshc
30 - qcom,qcs8300-ufshc
31 - qcom,sa8775p-ufshc
32 - qcom,sc7180-ufshc
33 - qcom,sc7280-ufshc
34 - qcom,sc8180x-ufshc
35 - qcom,sc8280xp-ufshc
36 - qcom,sdm845-ufshc
37 - qcom,sm6115-ufshc
38 - qcom,sm6125-ufshc
39 - qcom,sm6350-ufshc
40 - qcom,sm8150-ufshc
41 - qcom,sm8250-ufshc
42 - qcom,sm8350-ufshc
43 - qcom,sm8450-ufshc
44 - qcom,sm8550-ufshc
45 - qcom,sm8650-ufshc
46 - const: qcom,ufshc
47 - const: jedec,ufs-2.0
53 clock-names:
57 dma-coherent: true
63 interconnect-names:
65 - const: ufs-ddr
66 - const: cpu-ufs
75 phy-names:
77 - const: ufsphy
79 power-domains:
90 reg-names:
92 - const: std
93 - const: ice
95 required-opps:
101 '#reset-cells':
104 reset-names:
106 - const: rst
108 reset-gpios:
114 - compatible
115 - reg
118 - $ref: ufs-common.yaml
120 - if:
125 - qcom,sc7180-ufshc
131 clock-names:
133 - const: core_clk
134 - const: bus_aggr_clk
135 - const: iface_clk
136 - const: core_clk_unipro
137 - const: ref_clk
138 - const: tx_lane0_sync_clk
139 - const: rx_lane0_sync_clk
142 reg-names:
145 - if:
150 - qcom,msm8998-ufshc
151 - qcom,qcs8300-ufshc
152 - qcom,sa8775p-ufshc
153 - qcom,sc7280-ufshc
154 - qcom,sc8180x-ufshc
155 - qcom,sc8280xp-ufshc
156 - qcom,sm8250-ufshc
157 - qcom,sm8350-ufshc
158 - qcom,sm8450-ufshc
159 - qcom,sm8550-ufshc
160 - qcom,sm8650-ufshc
166 clock-names:
168 - const: core_clk
169 - const: bus_aggr_clk
170 - const: iface_clk
171 - const: core_clk_unipro
172 - const: ref_clk
173 - const: tx_lane0_sync_clk
174 - const: rx_lane0_sync_clk
175 - const: rx_lane1_sync_clk
179 reg-names:
182 - if:
187 - qcom,sdm845-ufshc
188 - qcom,sm6350-ufshc
189 - qcom,sm8150-ufshc
195 clock-names:
197 - const: core_clk
198 - const: bus_aggr_clk
199 - const: iface_clk
200 - const: core_clk_unipro
201 - const: ref_clk
202 - const: tx_lane0_sync_clk
203 - const: rx_lane0_sync_clk
204 - const: rx_lane1_sync_clk
205 - const: ice_core_clk
209 reg-names:
212 - reg-names
214 - if:
219 - qcom,msm8996-ufshc
225 clock-names:
227 - const: core_clk
228 - const: bus_clk
229 - const: bus_aggr_clk
230 - const: iface_clk
231 - const: core_clk_unipro
232 - const: core_clk_ice
233 - const: ref_clk
234 - const: tx_lane0_sync_clk
235 - const: rx_lane0_sync_clk
239 reg-names:
242 - if:
247 - qcom,qcs615-ufshc
248 - qcom,sm6115-ufshc
249 - qcom,sm6125-ufshc
255 clock-names:
257 - const: core_clk
258 - const: bus_aggr_clk
259 - const: iface_clk
260 - const: core_clk_unipro
261 - const: ref_clk
262 - const: tx_lane0_sync_clk
263 - const: rx_lane0_sync_clk
264 - const: ice_core_clk
268 reg-names:
271 - reg-names
273 # TODO: define clock bindings for qcom,msm8994-ufshc
275 - if:
277 - qcom,ice
297 - |
298 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
299 #include <dt-bindings/clock/qcom,rpmh.h>
300 #include <dt-bindings/gpio/gpio.h>
301 #include <dt-bindings/interconnect/qcom,sm8450.h>
302 #include <dt-bindings/interrupt-controller/arm-gic.h>
305 #address-cells = <2>;
306 #size-cells = <2>;
309 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
310 "jedec,ufs-2.0";
314 phy-names = "ufsphy";
315 lanes-per-direction = <2>;
316 #reset-cells = <1>;
317 resets = <&gcc GCC_UFS_PHY_BCR>;
318 reset-names = "rst";
319 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
321 vcc-supply = <&vreg_l7b_2p5>;
322 vcc-max-microamp = <1100000>;
323 vccq-supply = <&vreg_l9b_1p2>;
324 vccq-max-microamp = <1200000>;
326 power-domains = <&gcc UFS_PHY_GDSC>;
330 interconnect-names = "ufs-ddr", "cpu-ufs";
332 clock-names = "core_clk",
340 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
341 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
342 <&gcc GCC_UFS_PHY_AHB_CLK>,
343 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
345 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
346 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
347 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
348 freq-table-hz = <75000000 300000000>,