Lines Matching +full:cache +full:- +full:block
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
28 - $ref: extensions.yaml
29 - if:
35 - thead,c906
36 - thead,c910
37 - thead,c920
45 - items:
46 - enum:
47 - amd,mbv32
48 - andestech,ax45mp
49 - canaan,k210
50 - sifive,bullet0
51 - sifive,e5
52 - sifive,e7
53 - sifive,e71
54 - sifive,rocket0
55 - sifive,s7
56 - sifive,u5
57 - sifive,u54
58 - sifive,u7
59 - sifive,u74
60 - sifive,u74-mc
61 - spacemit,x60
62 - thead,c906
63 - thead,c908
64 - thead,c910
65 - thead,c920
66 - const: riscv
67 - items:
68 - enum:
69 - sifive,e51
70 - sifive,u54-mc
71 - const: sifive,rocket0
72 - const: riscv
73 - const: riscv # Simulator only
75 Identifies that the hart uses the RISC-V instruction set
78 mmu-type:
81 this hart. These values originate from the RISC-V Privileged
86 - riscv,sv32
87 - riscv,sv39
88 - riscv,sv48
89 - riscv,sv57
90 - riscv,none
96 riscv,cbom-block-size:
99 The blocksize in bytes for the Zicbom cache operations.
101 riscv,cbop-block-size:
104 The blocksize in bytes for the Zicbop cache operations.
106 riscv,cboz-block-size:
109 The blocksize in bytes for the Zicboz cache operations.
118 # RISC-V has multiple properties for cache op block sizes as the sizes
120 cache-op-block-size: false
121 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
122 timebase-frequency: false
124 interrupt-controller:
126 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
128 cpu-idle-states:
129 $ref: /schemas/types.yaml#/definitions/phandle-array
134 by this hart (see ./idle-states.yaml).
136 capacity-dmips-mhz:
138 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
139 DMIPS/MHz, relative to highest capacity-dmips-mhz
143 - required:
144 - riscv,isa
145 - required:
146 - riscv,isa-base
149 riscv,isa-base: [ "riscv,isa-extensions" ]
150 riscv,isa-extensions: [ "riscv,isa-base" ]
153 - interrupt-controller
158 - |
161 #address-cells = <1>;
162 #size-cells = <0>;
163 timebase-frequency = <1000000>;
165 clock-frequency = <0>;
168 i-cache-block-size = <64>;
169 i-cache-sets = <128>;
170 i-cache-size = <16384>;
172 riscv,isa-base = "rv64i";
173 riscv,isa-extensions = "i", "m", "a", "c";
175 cpu_intc0: interrupt-controller {
176 #interrupt-cells = <1>;
177 compatible = "riscv,cpu-intc";
178 interrupt-controller;
182 clock-frequency = <0>;
184 d-cache-block-size = <64>;
185 d-cache-sets = <64>;
186 d-cache-size = <32768>;
187 d-tlb-sets = <1>;
188 d-tlb-size = <32>;
190 i-cache-block-size = <64>;
191 i-cache-sets = <64>;
192 i-cache-size = <32768>;
193 i-tlb-sets = <1>;
194 i-tlb-size = <32>;
195 mmu-type = "riscv,sv39";
197 tlb-split;
198 riscv,isa-base = "rv64i";
199 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
201 cpu_intc1: interrupt-controller {
202 #interrupt-cells = <1>;
203 compatible = "riscv,cpu-intc";
204 interrupt-controller;
209 - |
212 #address-cells = <1>;
213 #size-cells = <0>;
218 mmu-type = "riscv,sv48";
219 riscv,isa-base = "rv64i";
220 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
222 interrupt-controller {
223 #interrupt-cells = <1>;
224 interrupt-controller;
225 compatible = "riscv,cpu-intc";