Lines Matching +full:rockchip +full:- +full:pcie +full:- +full:phy
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <[email protected]>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3576-naneng-combphy
17 - rockchip,rk3588-naneng-combphy
24 - description: reference clock
25 - description: apb clock
26 - description: pipe clock
28 clock-names:
30 - const: ref
31 - const: apb
32 - const: pipe
38 reset-names:
41 - const: phy
42 - const: apb
44 rockchip,enable-ssc:
47 The option SSC can be enabled for U3, SATA and PCIE.
50 rockchip,ext-refclk:
53 Many PCIe connections, especially backplane connections,
57 should be used by both ends of the PCIe link.
58 In PCIe mode one can choose to use an internal or an external reference
60 By default the internal clock is selected. The PCIe PHY provides a 100MHz
63 reference clock needs to be provided to the PCIe PHY.
65 rockchip,pipe-grf:
68 Some additional phy settings are accessed through GRF regs.
70 rockchip,pipe-phy-grf:
75 "#phy-cells":
79 - compatible
80 - reg
81 - clocks
82 - clock-names
83 - resets
84 - rockchip,pipe-grf
85 - rockchip,pipe-phy-grf
86 - "#phy-cells"
89 - if:
93 const: rockchip,rk3568-naneng-combphy
98 reset-names:
100 - if:
104 const: rockchip,rk3588-naneng-combphy
109 reset-names:
112 - reset-names
117 - |
118 #include <dt-bindings/clock/rk3568-cru.h>
121 compatible = "rockchip,rk3568-pipe-grf", "syscon";
126 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
130 combphy0: phy@fe820000 {
131 compatible = "rockchip,rk3568-naneng-combphy";
136 clock-names = "ref", "apb", "pipe";
137 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
138 assigned-clock-rates = <100000000>;
140 rockchip,pipe-grf = <&pipegrf>;
141 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
142 #phy-cells = <1>;