Lines Matching +full:rx +full:- +full:queues +full:- +full:to +full:- +full:use

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2021-2024 NXP
4 ---
5 $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Jan Petrous (OSS) <[email protected]>
16   the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
18   to the embedded SerDes for SGMII connectivity.
23       - const: nxp,s32g2-dwmac
24       - items:
25           - enum:
26               - nxp,s32g3-dwmac
27               - nxp,s32r45-dwmac
28           - const: nxp,s32g2-dwmac
32       - description: Main GMAC registers
33       - description: GMAC PHY mode control register
38   interrupt-names:
43       - description: Main GMAC clock
44       - description: Transmit clock
45       - description: Receive clock
46       - description: PTP reference clock
48   clock-names:
50       - const: stmmaceth
51       - const: tx
52       - const: rx
53       - const: ptp_ref
56   - clocks
57   - clock-names
60   - $ref: snps,dwmac.yaml#
65   - |
66     #include <dt-bindings/interrupt-controller/arm-gic.h>
67     #include <dt-bindings/interrupt-controller/irq.h>
68     #include <dt-bindings/phy/phy.h>
70       #address-cells = <2>;
71       #size-cells = <2>;
74         compatible = "nxp,s32g2-dwmac";
77         interrupt-parent = <&gic>;
79         interrupt-names = "macirq";
80         snps,mtl-rx-config = <&mtl_rx_setup>;
81         snps,mtl-tx-config = <&mtl_tx_setup>;
83         clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
84         phy-mode = "rgmii-id";
85         phy-handle = <&phy0>;
87         mtl_rx_setup: rx-queues-config {
88           snps,rx-queues-to-use = <5>;
91         mtl_tx_setup: tx-queues-config {
92           snps,tx-queues-to-use = <5>;
96           #address-cells = <1>;
97           #size-cells = <0>;
98           compatible = "snps,dwmac-mdio";
100           phy0: ethernet-phy@0 {