Lines Matching +full:gcc +full:- +full:msm8974
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bjorn Andersson <[email protected]>
11 - Konrad Dybcio <[email protected]>
20 - enum:
21 - qcom,sdhci-msm-v4
23 - items:
24 - enum:
25 - qcom,apq8084-sdhci
26 - qcom,ipq4019-sdhci
27 - qcom,ipq8074-sdhci
28 - qcom,msm8226-sdhci
29 - qcom,msm8953-sdhci
30 - qcom,msm8974-sdhci
31 - qcom,msm8976-sdhci
32 - qcom,msm8916-sdhci
33 - qcom,msm8992-sdhci
34 - qcom,msm8994-sdhci
35 - qcom,msm8996-sdhci
36 - qcom,msm8998-sdhci
37 - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
38 - items:
39 - enum:
40 - qcom,ipq5018-sdhci
41 - qcom,ipq5332-sdhci
42 - qcom,ipq5424-sdhci
43 - qcom,ipq6018-sdhci
44 - qcom,ipq9574-sdhci
45 - qcom,qcm2290-sdhci
46 - qcom,qcs404-sdhci
47 - qcom,qcs615-sdhci
48 - qcom,qdu1000-sdhci
49 - qcom,sar2130p-sdhci
50 - qcom,sc7180-sdhci
51 - qcom,sc7280-sdhci
52 - qcom,sc8280xp-sdhci
53 - qcom,sdm630-sdhci
54 - qcom,sdm670-sdhci
55 - qcom,sdm845-sdhci
56 - qcom,sdx55-sdhci
57 - qcom,sdx65-sdhci
58 - qcom,sdx75-sdhci
59 - qcom,sm6115-sdhci
60 - qcom,sm6125-sdhci
61 - qcom,sm6350-sdhci
62 - qcom,sm6375-sdhci
63 - qcom,sm8150-sdhci
64 - qcom,sm8250-sdhci
65 - qcom,sm8350-sdhci
66 - qcom,sm8450-sdhci
67 - qcom,sm8550-sdhci
68 - qcom,sm8650-sdhci
69 - qcom,x1e80100-sdhci
70 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
76 reg-names:
83 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
84 - description: SDC MMC clock, MCLK
85 - description: TCXO clock
86 - description: clock for Inline Crypto Engine
87 - description: SDCC bus voter clock
88 - description: reference clock for RCLK delay calibration
89 - description: sleep clock for RCLK delay calibration
91 clock-names:
94 - const: iface
95 - const: core
96 - const: xo
97 - enum: [ice, bus, cal, sleep]
98 - enum: [ice, bus, cal, sleep]
99 - enum: [ice, bus, cal, sleep]
100 - enum: [ice, bus, cal, sleep]
102 dma-coherent: true
107 interrupt-names:
109 - const: hc_irq
110 - const: pwr_irq
112 pinctrl-names:
115 - const: default
116 - const: sleep
118 pinctrl-0:
122 pinctrl-1:
129 qcom,ddr-config:
133 qcom,dll-config:
146 - description: data path, sdhc to ddr
147 - description: config path, cpu to sdhc
149 interconnect-names:
152 - const: sdhc-ddr
153 - const: cpu-sdhc
155 power-domains:
159 operating-points-v2: true
162 '^opp-table(-[a-z0-9]+)?$':
166 const: operating-points-v2
169 '^opp-?[0-9]+$':
171 - required-opps
174 - compatible
175 - reg
176 - clocks
177 - clock-names
178 - interrupts
181 - $ref: sdhci-common.yaml#
183 - if:
188 - qcom,sdhci-msm-v4
194 - description: Host controller register map
195 - description: SD Core register map
196 - description: CQE register map
197 - description: Inline Crypto Engine register map
198 reg-names:
201 - const: hc
202 - const: core
203 - const: cqhci
204 - const: ice
210 - description: Host controller register map
211 - description: CQE register map
212 - description: Inline Crypto Engine register map
213 reg-names:
216 - const: hc
217 - const: cqhci
218 - const: ice
223 - |
224 #include <dt-bindings/interrupt-controller/arm-gic.h>
225 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
226 #include <dt-bindings/clock/qcom,rpmh.h>
227 #include <dt-bindings/power/qcom,rpmhpd.h>
230 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
235 interrupt-names = "hc_irq", "pwr_irq";
237 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
238 <&gcc GCC_SDCC2_APPS_CLK>,
240 clock-names = "iface", "core", "xo";
242 qcom,dll-config = <0x0007642c>;
243 qcom,ddr-config = <0x80040868>;
244 power-domains = <&rpmhpd RPMHPD_CX>;
246 operating-points-v2 = <&sdhc2_opp_table>;
248 sdhc2_opp_table: opp-table {
249 compatible = "operating-points-v2";
251 opp-19200000 {
252 opp-hz = /bits/ 64 <19200000>;
253 required-opps = <&rpmhpd_opp_min_svs>;
256 opp-50000000 {
257 opp-hz = /bits/ 64 <50000000>;
258 required-opps = <&rpmhpd_opp_low_svs>;
261 opp-100000000 {
262 opp-hz = /bits/ 64 <100000000>;
263 required-opps = <&rpmhpd_opp_svs>;
266 opp-202000000 {
267 opp-hz = /bits/ 64 <202000000>;
268 required-opps = <&rpmhpd_opp_svs_l1>;