Lines Matching +full:mtk +full:- +full:vcodec +full:- +full:lat
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yunfei Dong <[email protected]>
19 +------------------------------------------------+-------------------------------------+
21 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
23 +------------||-------------||-------------------+---------------------||--------------+
24 || lat || | core workqueue <parent>
25 -------------||-------------||-------------------|---------------------||---------------
26 ||<------------||----------------HW index---------------->|| <child>
28 +-------------------------------------------------------------+
31 | (lat/lat soc/core0/core1) |
32 +-------------------------------------------------------------+
37 There are two workqueues in parent device: lat workqueue and core workqueue. They are used
38 to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer,
39 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
40 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
47 Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
48 platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
49 clock when lat start to work, don't have interrupt.
51 mt8195: lat soc HW + lat HW + core HW
52 mt8192: lat HW + core HW
57 - mediatek,mt8192-vcodec-dec
58 - mediatek,mt8186-vcodec-dec
59 - mediatek,mt8188-vcodec-dec
60 - mediatek,mt8195-vcodec-dec
65 - description: VDEC_SYS register space
66 - description: VDEC_RACING_CTRL register space
81 "#address-cells":
84 "#size-cells":
91 '^video-codec@[0-9a-f]+$':
97 - mediatek,mtk-vcodec-core
98 - mediatek,mtk-vcodec-lat
99 - mediatek,mtk-vcodec-lat-soc
119 clock-names:
123 assigned-clocks:
126 assigned-clock-parents:
129 power-domains:
133 - compatible
134 - reg
135 - iommus
136 - clocks
137 - clock-names
138 - assigned-clocks
139 - assigned-clock-parents
140 - power-domains
145 - compatible
146 - reg
147 - iommus
148 - mediatek,scp
149 - ranges
156 - mediatek,mtk-vcodec-core
157 - mediatek,mtk-vcodec-lat
161 - interrupts
164 - if:
169 - mediatek,mt8192-vcodec-dec
172 clock-names:
174 - const: sel
175 - const: soc-vdec
176 - const: soc-lat
177 - const: vdec
178 - const: top
180 - if:
185 - mediatek,mt8195-vcodec-dec
188 clock-names:
190 - const: sel
191 - const: vdec
192 - const: lat
193 - const: top
198 - |
199 #include <dt-bindings/interrupt-controller/arm-gic.h>
200 #include <dt-bindings/memory/mt8192-larb-port.h>
201 #include <dt-bindings/interrupt-controller/irq.h>
202 #include <dt-bindings/clock/mt8192-clk.h>
203 #include <dt-bindings/power/mt8192-power.h>
206 #address-cells = <2>;
207 #size-cells = <2>;
210 video-codec@16000000 {
211 compatible = "mediatek,mt8192-vcodec-dec";
214 #address-cells = <2>;
215 #size-cells = <2>;
218 video-codec@10000 {
219 compatible = "mediatek,mtk-vcodec-lat";
235 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
236 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
237 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
238 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
241 video-codec@25000 {
242 compatible = "mediatek,mtk-vcodec-core";
261 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
262 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
263 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
264 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;