Lines Matching +full:r9a07g044 +full:- +full:adc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L ADC
10 - Lad Prabhakar <prabhakar.mahadev-[email protected]>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
15 Conversions can be performed in single or repeat mode. Result of the ADC is
16 stored in a 32-bit data register corresponding to each channel.
21 - items:
22 - enum:
23 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
24 - renesas,r9a07g044-adc # RZ/G2L
25 - renesas,r9a07g054-adc # RZ/V2L
26 - const: renesas,rzg2l-adc
27 - items:
28 - const: renesas,r9a08g045-adc # RZ/G3S
38 - description: converter clock
39 - description: peripheral clock
41 clock-names:
43 - const: adclk
44 - const: pclk
46 power-domains:
52 reset-names:
54 - const: presetn
55 - const: adrst-n
57 '#address-cells':
60 '#size-cells':
63 "#io-channel-cells":
67 - compatible
68 - reg
69 - interrupts
70 - clocks
71 - clock-names
72 - power-domains
73 - resets
74 - reset-names
77 "^channel@[0-8]$":
78 $ref: adc.yaml
81 Represents the external channels which are connected to the ADC.
91 - reg
96 - if:
100 const: renesas,r9a07g043-adc
103 "^channel@[2-8]$": false
104 "^channel@[0-1]$":
109 - if:
114 - renesas,r9a07g044-adc
115 - renesas,r9a07g054-adc
119 "^channel@[0-7]$":
127 - |
128 #include <dt-bindings/clock/r9a07g044-cpg.h>
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
131 adc: adc@10059000 {
132 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
137 clock-names = "adclk", "pclk";
138 power-domains = <&cpg>;
141 reset-names = "presetn", "adrst-n";
143 #address-cells = <1>;
144 #size-cells = <0>;