1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L ADC
8
9maintainers:
10  - Lad Prabhakar <[email protected]>
11
12description: |
13  A/D Converter block is a successive approximation analog-to-digital converter
14  with a 12-bit accuracy. Up to eight analog input channels can be selected.
15  Conversions can be performed in single or repeat mode. Result of the ADC is
16  stored in a 32-bit data register corresponding to each channel.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - renesas,r9a07g043-adc   # RZ/G2UL and RZ/Five
24              - renesas,r9a07g044-adc   # RZ/G2L
25              - renesas,r9a07g054-adc   # RZ/V2L
26          - const: renesas,rzg2l-adc
27      - items:
28          - const: renesas,r9a08g045-adc  # RZ/G3S
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    items:
38      - description: converter clock
39      - description: peripheral clock
40
41  clock-names:
42    items:
43      - const: adclk
44      - const: pclk
45
46  power-domains:
47    maxItems: 1
48
49  resets:
50    maxItems: 2
51
52  reset-names:
53    items:
54      - const: presetn
55      - const: adrst-n
56
57  '#address-cells':
58    const: 1
59
60  '#size-cells':
61    const: 0
62
63  "#io-channel-cells":
64    const: 1
65
66required:
67  - compatible
68  - reg
69  - interrupts
70  - clocks
71  - clock-names
72  - power-domains
73  - resets
74  - reset-names
75
76patternProperties:
77  "^channel@[0-8]$":
78    $ref: adc.yaml
79    type: object
80    description: |
81      Represents the external channels which are connected to the ADC.
82
83    properties:
84      reg:
85        description: |
86          The channel number.
87        minimum: 0
88        maximum: 8
89
90    required:
91      - reg
92
93    additionalProperties: false
94
95allOf:
96  - if:
97      properties:
98        compatible:
99          contains:
100            const: renesas,r9a07g043-adc
101    then:
102      patternProperties:
103        "^channel@[2-8]$": false
104        "^channel@[0-1]$":
105          properties:
106            reg:
107              maximum: 1
108
109  - if:
110      properties:
111        compatible:
112          contains:
113            enum:
114              - renesas,r9a07g044-adc
115              - renesas,r9a07g054-adc
116    then:
117      patternProperties:
118        "^channel@[8]$": false
119        "^channel@[0-7]$":
120          properties:
121            reg:
122              maximum: 7
123
124additionalProperties: false
125
126examples:
127  - |
128    #include <dt-bindings/clock/r9a07g044-cpg.h>
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130
131    adc: adc@10059000 {
132      compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
133      reg = <0x10059000 0x400>;
134      interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
135      clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
136               <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
137      clock-names = "adclk", "pclk";
138      power-domains = <&cpg>;
139      resets = <&cpg R9A07G044_ADC_PRESETN>,
140               <&cpg R9A07G044_ADC_ADRST_N>;
141      reset-names = "presetn", "adrst-n";
142
143      #address-cells = <1>;
144      #size-cells = <0>;
145
146      channel@0 {
147        reg = <0>;
148      };
149      channel@1 {
150        reg = <1>;
151      };
152      channel@2 {
153        reg = <2>;
154      };
155      channel@3 {
156        reg = <3>;
157      };
158      channel@4 {
159        reg = <4>;
160      };
161      channel@5 {
162        reg = <5>;
163      };
164      channel@6 {
165        reg = <6>;
166      };
167      channel@7 {
168        reg = <7>;
169      };
170    };
171