Lines Matching +full:sc7180 +full:- +full:dp
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <[email protected]>
11 - Abhinav Kumar <[email protected]>
20 - enum:
21 - qcom,sa8775p-dp
22 - qcom,sc7180-dp
23 - qcom,sc7280-dp
24 - qcom,sc7280-edp
25 - qcom,sc8180x-dp
26 - qcom,sc8180x-edp
27 - qcom,sc8280xp-dp
28 - qcom,sc8280xp-edp
29 - qcom,sdm845-dp
30 - qcom,sm8350-dp
31 - qcom,sm8650-dp
32 - items:
33 - enum:
34 - qcom,sm6350-dp
35 - qcom,sm8150-dp
36 - qcom,sm8250-dp
37 - qcom,sm8450-dp
38 - qcom,sm8550-dp
39 - const: qcom,sm8350-dp
44 - description: ahb register block
45 - description: aux register block
46 - description: link register block
47 - description: p0 register block
48 - description: p1 register block
55 - description: AHB clock to enable register access
56 - description: Display Port AUX clock
57 - description: Display Port Link clock
58 - description: Link interface clock between DP and PHY
59 - description: Display Port Pixel clock
61 clock-names:
63 - const: core_iface
64 - const: core_aux
65 - const: ctrl_link
66 - const: ctrl_link_iface
67 - const: stream_pixel
69 assigned-clocks:
71 - description: link clock source
72 - description: pixel clock source
74 assigned-clock-parents:
76 - description: phy 0 parent
77 - description: phy 1 parent
82 phy-names:
84 - const: dp
86 operating-points-v2: true
88 opp-table:
91 power-domains:
94 aux-bus:
95 $ref: /schemas/display/dp-aux-bus.yaml#
97 data-lanes:
98 $ref: /schemas/types.yaml#/definitions/uint32-array
105 "#sound-dai-cells":
108 vdda-0p9-supply:
110 vdda-1p2-supply:
121 $ref: /schemas/graph.yaml#/$defs/port-base
126 $ref: /schemas/media/video-interfaces.yaml#
129 data-lanes:
135 link-frequencies:
142 - port@0
143 - port@1
146 - compatible
147 - reg
148 - interrupts
149 - clocks
150 - clock-names
151 - phys
152 - phy-names
153 - power-domains
154 - ports
157 # AUX BUS does not exist on DP controllers
158 # Audio output also is present only on DP output
159 # p1 regions is present on DP, but not on eDP
160 - if:
165 - qcom,sc7280-edp
166 - qcom,sc8180x-edp
167 - qcom,sc8280xp-edp
170 "#sound-dai-cells": false
173 aux-bus: false
177 - "#sound-dai-cells"
182 - |
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
185 #include <dt-bindings/power/qcom-rpmpd.h>
187 displayport-controller@ae90000 {
188 compatible = "qcom,sc7180-dp";
194 interrupt-parent = <&mdss>;
201 clock-names = "core_iface", "core_aux",
205 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
208 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
211 phy-names = "dp";
213 #sound-dai-cells = <0>;
215 power-domains = <&rpmhpd SC7180_CX>;
218 #address-cells = <1>;
219 #size-cells = <0>;
224 remote-endpoint = <&dpu_intf0_out>;
231 remote-endpoint = <&typec>;
232 data-lanes = <0 1>;
233 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;