Lines Matching +full:x1e80100 +full:- +full:gcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <[email protected]>
17 include/dt-bindings/clock/qcom,sar2130p-gpucc.h
18 include/dt-bindings/clock/qcom,sm4450-gpucc.h
19 include/dt-bindings/clock/qcom,sm8450-gpucc.h
20 include/dt-bindings/clock/qcom,sm8550-gpucc.h
21 include/dt-bindings/reset/qcom,sm8450-gpucc.h
22 include/dt-bindings/reset/qcom,sm8650-gpucc.h
23 include/dt-bindings/reset/qcom,x1e80100-gpucc.h
28 - qcom,sar2130p-gpucc
29 - qcom,sm4450-gpucc
30 - qcom,sm8450-gpucc
31 - qcom,sm8475-gpucc
32 - qcom,sm8550-gpucc
33 - qcom,sm8650-gpucc
34 - qcom,x1e80100-gpucc
35 - qcom,x1p42100-gpucc
39 - description: Board XO source
40 - description: GPLL0 main branch source
41 - description: GPLL0 div branch source
44 - compatible
45 - clocks
46 - '#power-domain-cells'
49 - $ref: qcom,gcc.yaml#
54 - |
55 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
56 #include <dt-bindings/clock/qcom,rpmh.h>
59 #address-cells = <2>;
60 #size-cells = <2>;
62 clock-controller@3d90000 {
63 compatible = "qcom,sm8450-gpucc";
66 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
67 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
68 #clock-cells = <1>;
69 #reset-cells = <1>;
70 #power-domain-cells = <1>;