101 			 *    - Data cache is 4-way set-associative.  in cpuinfo_arm_decode_cache()
102 			 *    - Instruction cache is 2-way set-associative.  in cpuinfo_arm_decode_cache()
150 				 * Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size"  in cpuinfo_arm_decode_cache()
166 			 *    - 2-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
170 			 *    - 4-way set-associative data cache.  in cpuinfo_arm_decode_cache()
177 			 *      - 8-way set-associative cache structure  in cpuinfo_arm_decode_cache()
229 			 *     - 4-way set associative cache structure  in cpuinfo_arm_decode_cache()
235 			 *     - 8-way set associative cache structure  in cpuinfo_arm_decode_cache()
278 			 *     - Both caches are 4-way set-associative.  in cpuinfo_arm_decode_cache()
317 				/* OMAP4460 in Pandaboard ES has 16-way set-associative L2 cache */  in cpuinfo_arm_decode_cache()
327 			 *     - 32KB 2-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
330 			 *     - 32KB 2-way set-associative data cache.  in cpuinfo_arm_decode_cache()
336 			 *     - 16-way set-associative cache structure.  in cpuinfo_arm_decode_cache()
382 			 *     - 4-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
386 			 *     - 4-way set-associative data cache.  in cpuinfo_arm_decode_cache()
392 			 *     - 16-way set-associative cache structure.  in cpuinfo_arm_decode_cache()
430 			 *      - is 2-way set associative.  in cpuinfo_arm_decode_cache()
437 			 *      - is 4-way set associative.  in cpuinfo_arm_decode_cache()
442 			 *   The L2 cache is 8-way set associative.  in cpuinfo_arm_decode_cache()
479 			 *    - 2-way set associative L1 Instruction cache.  in cpuinfo_arm_decode_cache()
483 			 *    - 4-way set associative L1 Data cache.  in cpuinfo_arm_decode_cache()
490 			 *      - 16-way set-associative cache structure.  in cpuinfo_arm_decode_cache()
682 			 *    - 4-way set associative L1 instruction cache.  in cpuinfo_arm_decode_cache()
686 			 *    - 4-way set associative L1 data cache.  in cpuinfo_arm_decode_cache()
691 …*    - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256K…  in cpuinfo_arm_decode_cache()
798 			 *    - 48KB 3-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
802 			 *    - 32KB 2-way set-associative data cache.  in cpuinfo_arm_decode_cache()
809 			 *    - 16-way set-associative cache structure.  in cpuinfo_arm_decode_cache()
853 			 *    - 4-way set associative L1 instruction cache.  in cpuinfo_arm_decode_cache()
857 			 *    - 4-way set associative L1 data cache.  in cpuinfo_arm_decode_cache()
862 …*    - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB, or 256…  in cpuinfo_arm_decode_cache()
905 			 *    - 48KB 3-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
909 			 *    - 32KB 2-way set-associative data cache.  in cpuinfo_arm_decode_cache()
918 			 *    - 16-way set-associative cache structure.  in cpuinfo_arm_decode_cache()
979 			 *    - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
983 …*    - ...the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurat…  in cpuinfo_arm_decode_cache()
984 			 *      and a 16-way set associative PIPT cache (for 64KB configurations).  in cpuinfo_arm_decode_cache()
991 			 *      - A 16-way, set-associative structure.  in cpuinfo_arm_decode_cache()
1063 			 *    - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache.  in cpuinfo_arm_decode_cache()
1068 			 *    - Physically Indexed, Physically Tagged (PIPT), 16-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1074 			 *    - An 8-way set associative L2 cache with a configurable size of 256KB or 512KB.  in cpuinfo_arm_decode_cache()
1128 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1134 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1140 			 *    - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB.  in cpuinfo_arm_decode_cache()
1201 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1207 			 *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1213 …*    - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache …  in cpuinfo_arm_decode_cache()
1254                          *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1260                          *      Physically Tagged (PIPT) 4-way set-associative L1 data cache.  in cpuinfo_arm_decode_cache()
1266 …*    - An 8-way set associative L2 cache with a configurable size of 256KB, 512KB, or 1024KB. Cach…  in cpuinfo_arm_decode_cache()
1307 			 *    We interpret it as L2 cache being 4-way set-associative on single-core Scorpion.  in cpuinfo_arm_decode_cache()
1338 			 * - L1 Data cache = 16 KB. 64 B/line, 4-way [1]  in cpuinfo_arm_decode_cache()
1339 			 * - L1 Instruction cache = 16 KB, 4-way [1]  in cpuinfo_arm_decode_cache()
1340 …	 * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1]  in cpuinfo_arm_decode_cache()
1341 			 * - L2	= 1MB (dual core) or 2MB (quad core), 8-way set associative [2]  in cpuinfo_arm_decode_cache()
1404 …* The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data ca…  in cpuinfo_arm_decode_cache()
1405 			 * and a 2MB, 16-way level 2 cache, all of which can service both cores. [1]  in cpuinfo_arm_decode_cache()
1433 …* - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1]  in cpuinfo_arm_decode_cache()
1617 	 * There is no precise way to detect cache size on ARM/ARM64, and cache size reported by cpuinfo  in cpuinfo_arm_compute_max_cache_size()